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Rocket Core Generator
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================================================================
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Rocket Core
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===========
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Rocket is a 6-stage single-issue in-order pipeline that executes the 64-bit
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scalar RISC-V ISA. Rocket implements an MMU that supports page-based virtual
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single- and double-precision floating-point operations, including fused
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multiply-add.
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We plan to open-source our Rocket core generator written in Chisel in the near
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future. We are currently in the process of cleaning up the repository. Please stay tuned.
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Currently, a Rocket core with an 8 KB direct-mapped L1 instruction cache
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and an 8 KB direct-mapped L1 data cache has been instantiated and committed to
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the fpga-zynq infrastructure repository. A copy of the generated Verilog is available
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[here](https://raw.githubusercontent.com/ucb-bar/fpga-zynq/master/hw/src/verilog/Slave.v).
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This repository is not intended to be a self-running repository. To
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instantiate a Rocket core, please use the Rocket chip generator found in the
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rocket-chip git repository.
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The following table compares a 32-bit ARM Cortex-A5 core to a 64-bit RISC-V
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Rocket core built in the same TSMC process (40GPLUS). Fourth column is the
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