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Commit Graph

626 Commits

Author SHA1 Message Date
20e1de08da Avoid chisel2 pitfall
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3.  D'oh.
2016-06-01 23:35:49 -07:00
5629fb62bf Avoid bitwise sub-assignment 2016-06-01 21:59:02 -07:00
9518b3d589 Fix arithmetic in ROM row count 2016-06-01 21:59:02 -07:00
8e80d1ec80 Avoid floating-point arithmetic where integers suffice 2016-06-01 21:59:02 -07:00
11b3cee07a Ahb tweaks (#50)
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
2016-06-01 16:42:39 -07:00
740a6073f6 Add Debug Module (#49)
* Add Debug Module

* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents

* [debug] Update Debug ROM contents to match updated addresses
2016-06-01 16:33:33 -07:00
e8408f0a8a fix HastiRAM 2016-06-01 10:33:59 -07:00
6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
8afdd7e3da Work around PutBlocks draining into data array prematurely 2016-05-26 23:08:05 -07:00
391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect
We should eventually parameterize this, of course.
2016-05-26 16:10:42 -07:00
b6d26e90f8 Add generic TileLink width adapter 2016-05-26 15:59:42 -07:00
8139f71dfb Work around Chisel2 bug
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
2016-05-26 12:37:31 -07:00
22568de5f3 Work around another zero-width wire limitation 2016-05-25 21:42:02 -07:00
e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
7f1792cba3 ahb: backport bridge to chisel2
Closes #47
2016-05-25 13:40:24 -07:00
c49cb10c74 Merge pull request #42 from terpstra/ahb
Ahb
2016-05-24 17:02:15 -07:00
88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches 2016-05-24 15:47:09 -07:00
a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00
ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) 2016-05-24 14:58:27 -07:00
00d31dc5c5 bram: use new hasti definitions 2016-05-24 13:35:16 -07:00
ee0acc1d07 Fix BRAM assertion condition 2016-05-23 13:19:53 -07:00
3e0b5d6fd9 Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,
but would otherwise be allocated.

Closes #45
2016-05-20 16:35:30 -07:00
fd83d20857 Use a def instead of a lazy val in ManagerCoherenceAgent.
Prevents C++ emulator from randomizing inputs in unit testing.

Closes #44
2016-05-20 16:31:12 -07:00
d69446e177 Add config classes to drive unit testing of L2 TileLink agents.
Closes #43
2016-05-20 16:15:43 -07:00
4f84d8f757 make sure to hook up finish in ClientTileLinkEnqueuer 2016-05-18 13:13:34 -07:00
f138819992 fix order of assignments in ManagerTileLinkNetworkPort 2016-05-11 16:45:00 -07:00
533b229175 Improve PLIC QoR 2016-05-10 17:03:56 -07:00
e15e9c5085 First draft of interrupt controller 2016-05-10 00:25:13 -07:00
14a6e470c9 transform ids in TL -> NASTI converter if necessary 2016-05-07 21:19:27 -07:00
1ed6d6646d move NastiROM and HastiRAM into rom.scala and bram.scala 2016-05-06 11:31:22 -07:00
77e859760c add a Hasti RAM alongside the Nasti ROM 2016-05-06 11:31:22 -07:00
f26c422544 assert that TileLink router has valid route 2016-05-03 12:18:06 -07:00
cc4102f8de Add trivial version of PRCI block
It doesn't really do anything besides deliver deliver IPIs yet.
2016-05-02 17:49:10 -07:00
72731de25a Take a stab at the PRCI-Rocket interface 2016-05-02 15:20:33 -07:00
695c4c5096 Support both Get and GetBlock on ROMSlave 2016-04-30 17:34:12 -07:00
6f052a740c Add TileLink BRAM slave 2016-04-29 14:10:44 -07:00
1df68a25fd Address Map refactoring 2016-04-28 16:08:58 -07:00
ed5bdf3c23 print the base address of each SCR as indicated 2016-04-28 16:31:56 +01:00
81ff127dc3 Clean up TileLinkRecursiveInterconnect a bit 2016-04-27 14:53:11 -07:00
87cecc336f Add new RTC as TileLink slave, not AXI master 2016-04-27 11:55:35 -07:00
eb0b5ec61e Remove stats CSR 2016-04-27 00:16:21 -07:00
9044a4a4b7 Replace NastiROM with ROMSlave, which uses TileLink
I'm not wedded to the name.
2016-04-27 00:15:30 -07:00
356efe2fd5 Simplify TileLink Narrower
It's not necessary to use addr_beat to determine where to put the Grant
data.  Just stripe it across all lanes.

This also gets rid of a dependence on addr_beat in Grant.  If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
2016-04-26 16:44:54 -07:00
f6e44b1348 avoid logical to physical header conversion overflow 2016-04-22 17:47:34 +01:00
f9de99ed40 changes to match junctions no-mmio-base 2016-04-21 15:35:37 -07:00
9b3faff5a5 add id field to write data channel in TL -> AXI converter 2016-04-19 09:46:31 -07:00
152645b1bc use manager_id instead of client_id in GrantFromSrc and FinishToDst 2016-04-07 11:20:16 -07:00
f88b6932ce don't add pending reads if data is already available 2016-04-06 15:43:21 -07:00
31e145eaf0 fix BroadcastHub allocation and routing 2016-04-05 16:21:18 -07:00