2014-09-12 19:15:04 +02:00
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// See LICENSE for license details.
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2014-09-02 22:51:57 +02:00
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package rocketchip
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2014-08-23 10:26:03 +02:00
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import Chisel._
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2015-07-30 02:56:19 +02:00
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import junctions._
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2016-06-28 22:16:48 +02:00
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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2016-07-07 01:54:58 +02:00
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import uncore.converters._
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2014-08-23 10:26:03 +02:00
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import rocket._
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import rocket.Util._
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2015-11-10 22:39:08 +01:00
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import groundtest._
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2015-06-26 08:17:35 +02:00
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import scala.math.max
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2016-07-09 00:29:35 +02:00
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import scala.collection.mutable.ListBuffer
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2015-07-13 23:54:26 +02:00
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import DefaultTestSuites._
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2016-04-22 04:37:08 +02:00
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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2014-08-23 10:26:03 +02:00
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2016-03-16 22:21:47 +01:00
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object ConfigUtils {
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def max_int(values: Int*): Int = {
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values.reduce((a, b) => max(a, b))
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}
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}
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import ConfigUtils._
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2016-05-25 20:08:11 +02:00
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class BaseConfig extends Config (
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2014-10-06 22:43:40 +02:00
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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2016-04-29 01:15:31 +02:00
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lazy val internalIOAddrMap: AddrMap = {
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2016-05-03 03:08:33 +02:00
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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2016-06-04 02:29:05 +02:00
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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2016-06-06 13:51:55 +02:00
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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2016-05-03 03:08:33 +02:00
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new AddrMap(entries)
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2015-11-26 06:10:09 +01:00
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}
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2016-06-04 02:29:05 +02:00
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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2016-07-05 21:40:14 +02:00
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val memSize = 0x10000000L
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2016-07-12 03:10:42 +02:00
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val io = new AddrMap(AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries)
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2016-05-01 05:59:36 +02:00
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val addrMap = AddrMap(
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2016-07-05 21:40:14 +02:00
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AddrMapEntry("io", io),
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2016-06-04 02:29:05 +02:00
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AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
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2016-05-01 05:59:36 +02:00
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2016-06-04 02:29:05 +02:00
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Dump("MEM_BASE", addrMap("mem").start)
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2016-04-29 01:15:31 +02:00
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Dump("MEM_SIZE", memSize)
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2016-06-04 02:29:05 +02:00
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addrMap
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2016-04-29 01:15:31 +02:00
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}
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2016-03-15 02:03:33 +01:00
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def makeConfigString() = {
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2016-06-04 02:29:05 +02:00
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val addrMap = globalAddrMap
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2016-06-06 13:51:55 +02:00
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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2016-05-10 09:27:31 +02:00
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val plicInfo = site(PLICKey)
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2016-03-15 02:03:33 +01:00
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val xLen = site(XLen)
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val res = new StringBuilder
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2016-05-10 09:27:31 +02:00
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
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res append s" ndevs ${plicInfo.nDevices};\n"
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res append "};\n"
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2016-04-27 23:57:54 +02:00
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res append "rtc {\n"
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2016-06-28 08:08:29 +02:00
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res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
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2016-04-27 23:57:54 +02:00
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res append "};\n"
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2016-03-15 02:03:33 +01:00
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res append "ram {\n"
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res append " 0 {\n"
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2016-04-29 01:15:31 +02:00
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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2016-06-04 02:29:05 +02:00
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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2016-03-15 02:03:33 +01:00
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res append " };\n"
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res append "};\n"
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res append "core {\n"
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for (i <- 0 until site(NTiles)) {
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2016-05-25 20:08:11 +02:00
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val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(UseFPU)) "fd" else ""}"
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2016-03-15 02:03:33 +01:00
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res append s" $i {\n"
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res append " 0 {\n"
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2016-04-29 01:15:31 +02:00
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res append s" isa $isa;\n"
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2016-06-28 08:08:29 +02:00
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res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
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res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
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2016-05-10 09:27:31 +02:00
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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2016-05-13 20:22:46 +02:00
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if (site(UseVM)) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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2016-05-10 09:27:31 +02:00
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res append s" };\n"
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2016-03-15 02:03:33 +01:00
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res append " };\n"
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res append " };\n"
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}
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res append "};\n"
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res append '\u0000'
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res.toString.getBytes
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2015-09-25 18:41:19 +02:00
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}
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2016-07-01 03:20:43 +02:00
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lazy val innerDataBits = 64
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2016-06-08 19:16:04 +02:00
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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2014-10-06 22:43:40 +02:00
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pname match {
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//Memory Parameters
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case PAddrBits => 32
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2015-06-26 08:17:35 +02:00
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case PgIdxBits => 12
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8)
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case VPNBits => site(PgLevels) * site(PgLevelBits)
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2014-10-06 22:43:40 +02:00
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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2015-06-26 08:17:35 +02:00
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case VAddrBits => site(VPNBits) + site(PgIdxBits)
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case ASIdBits => 7
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2016-05-08 06:26:03 +02:00
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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2016-02-27 20:41:28 +01:00
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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2016-02-26 10:29:38 +01:00
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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2015-10-13 21:46:23 +02:00
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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2015-10-14 20:33:18 +02:00
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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2014-10-06 22:43:40 +02:00
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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2015-06-26 08:17:35 +02:00
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case NTLBEntries => findBy(CacheName)
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2015-11-22 01:11:22 +01:00
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case CacheIdBits => findBy(CacheName)
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2016-02-29 23:49:18 +01:00
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case SplitMetadata => findBy(CacheName)
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2014-10-06 22:43:40 +02:00
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case "L1I" => {
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2015-06-26 08:17:35 +02:00
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case NSets => Knob("L1I_SETS") //64
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case NWays => Knob("L1I_WAYS") //4
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2016-04-02 01:40:30 +02:00
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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2015-06-26 08:17:35 +02:00
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case NTLBEntries => 8
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2015-11-22 01:11:22 +01:00
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case CacheIdBits => 0
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2016-03-10 23:17:41 +01:00
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case SplitMetadata => false
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2014-10-06 22:43:40 +02:00
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}:PF
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case "L1D" => {
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2015-06-26 08:17:35 +02:00
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case NSets => Knob("L1D_SETS") //64
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2014-10-06 22:43:40 +02:00
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case NWays => Knob("L1D_WAYS") //4
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2016-04-02 01:40:30 +02:00
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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2015-06-26 08:17:35 +02:00
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case NTLBEntries => 8
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2015-11-22 01:11:22 +01:00
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case CacheIdBits => 0
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2016-03-10 23:17:41 +01:00
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case SplitMetadata => false
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2014-10-06 22:43:40 +02:00
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}:PF
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(NWays))
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2015-06-26 08:17:35 +02:00
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case AmoAluOperandBits => site(XLen)
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2014-10-06 22:43:40 +02:00
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//L1InstCache
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2015-10-06 19:47:38 +02:00
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case BtbKey => BtbParameters()
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2014-10-06 22:43:40 +02:00
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//L1DataCache
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2015-06-26 08:17:35 +02:00
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case WordBits => site(XLen)
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2014-10-06 22:43:40 +02:00
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case LRSCCycles => 32
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2015-06-26 08:17:35 +02:00
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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2015-10-14 08:44:05 +02:00
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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2015-11-22 01:11:22 +01:00
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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2015-10-06 19:47:38 +02:00
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Module(new L2BroadcastHub()(p.alterPartial({
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2015-10-14 08:44:05 +02:00
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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2016-06-14 01:24:01 +02:00
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case NCachedTileLinkPorts => 1
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case NUncachedTileLinkPorts => 1
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2014-10-06 22:43:40 +02:00
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//Tile Constants
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2015-07-13 23:54:26 +02:00
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case BuildTiles => {
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2016-03-11 02:40:21 +01:00
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val (rvi, rvu) =
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2016-07-22 20:36:45 +02:00
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if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
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else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
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2016-03-11 02:40:21 +01:00
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TestGeneration.addSuites(rvi.map(_("p")))
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2016-05-01 05:59:36 +02:00
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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2016-07-22 20:36:45 +02:00
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TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
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2015-10-06 19:47:38 +02:00
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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2016-06-14 01:24:01 +02:00
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Module(new RocketTile(resetSignal = r)(p.alterPartial({
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case TLId => "L1toL2"
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case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
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})))
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2015-10-06 19:47:38 +02:00
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}
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2015-07-13 23:54:26 +02:00
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}
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2015-11-26 01:02:54 +01:00
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case BuildRoCC => Nil
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2015-12-02 02:55:07 +01:00
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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2016-02-25 07:52:02 +01:00
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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2016-01-15 00:10:40 +01:00
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case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
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2014-10-06 22:43:40 +02:00
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//Rocket Core Constants
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2016-07-30 01:36:07 +02:00
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case FetchWidth => if (site(UseCompressed)) 2 else 1
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2014-10-06 22:43:40 +02:00
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case RetireWidth => 1
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case UseVM => true
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2016-05-26 00:40:53 +02:00
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case UseUser => true
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2016-06-02 19:53:41 +02:00
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case UseDebug => true
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2016-07-18 23:09:10 +02:00
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case AsyncDebugBus => false
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2016-06-09 05:21:21 +02:00
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case NBreakpoints => 1
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2015-09-28 22:55:55 +02:00
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case UsePerfCounters => true
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2014-10-06 22:43:40 +02:00
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case FastLoadWord => true
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case FastLoadByte => false
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2016-07-16 00:40:17 +02:00
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case MulUnroll => 8
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2016-07-15 23:40:37 +02:00
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case DivEarlyOut => true
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2015-06-26 08:17:35 +02:00
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case XLen => 64
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2015-10-21 00:04:39 +02:00
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case UseFPU => {
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2016-05-01 05:59:36 +02:00
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val env = if(site(UseVM)) List("p","v") else List("p")
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2016-07-08 04:34:03 +02:00
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TestGeneration.addSuite(rv32udBenchmarks)
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2016-06-23 01:14:02 +02:00
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if(site(FDivSqrt)) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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2016-07-08 04:34:03 +02:00
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} else {
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2016-06-23 01:14:02 +02:00
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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}
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2015-10-21 00:04:39 +02:00
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true
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2015-07-14 03:56:18 +02:00
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}
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2016-05-25 20:08:11 +02:00
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case UseAtomics => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
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true
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}
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2016-07-30 01:36:07 +02:00
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case UseCompressed => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
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true
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}
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2016-05-10 09:27:31 +02:00
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case NExtInterrupts => 2
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2016-07-18 23:09:10 +02:00
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case AsyncMMIOChannels => false
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2016-07-05 21:40:14 +02:00
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case ExtMMIOPorts => AddrMap()
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/*
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AddrMap(
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AddrMapEntry("cfg", MemRange(0x50000000L, 0x04000000L, MemAttr(AddrMapProt.RW))),
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AddrMapEntry("ext", MemRange(0x60000000L, 0x20000000L, MemAttr(AddrMapProt.RWX))))
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*/
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2016-05-26 23:14:56 +02:00
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case NExtMMIOAXIChannels => 0
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2016-05-26 23:49:27 +02:00
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case NExtMMIOAHBChannels => 0
|
2016-07-01 03:20:43 +02:00
|
|
|
case NExtMMIOTLChannels => 0
|
2016-07-18 23:09:10 +02:00
|
|
|
case AsyncBusChannels => false
|
2016-07-05 21:43:33 +02:00
|
|
|
case NExtBusAXIChannels => 0
|
2016-06-04 02:29:05 +02:00
|
|
|
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
|
2016-06-02 19:53:41 +02:00
|
|
|
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
|
2015-06-26 08:17:35 +02:00
|
|
|
case FDivSqrt => true
|
2014-10-06 22:43:40 +02:00
|
|
|
case SFMALatency => 2
|
|
|
|
case DFMALatency => 3
|
2016-07-30 01:36:07 +02:00
|
|
|
case CoreInstBits => if (site(UseCompressed)) 16 else 32
|
2015-06-26 08:17:35 +02:00
|
|
|
case CoreDataBits => site(XLen)
|
|
|
|
case NCustomMRWCSRs => 0
|
2016-05-01 05:59:36 +02:00
|
|
|
case ResetVector => BigInt(0x1000)
|
|
|
|
case MtvecInit => BigInt(0x1010)
|
|
|
|
case MtvecWritable => true
|
2014-10-06 22:43:40 +02:00
|
|
|
//Uncore Paramters
|
2015-07-08 02:26:07 +02:00
|
|
|
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
|
2015-10-14 08:44:05 +02:00
|
|
|
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
|
|
|
|
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
|
|
|
|
log2Up(site(TLKey(site(TLId))).nClients)
|
2016-05-25 00:59:59 +02:00
|
|
|
case HastiId => "Ext"
|
2016-05-25 00:59:59 +02:00
|
|
|
case HastiKey("TL") =>
|
|
|
|
HastiParameters(
|
|
|
|
addrBits = site(PAddrBits),
|
|
|
|
dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
|
2016-05-25 00:59:59 +02:00
|
|
|
case HastiKey("Ext") =>
|
|
|
|
HastiParameters(
|
|
|
|
addrBits = site(PAddrBits),
|
|
|
|
dataBits = site(XLen))
|
2016-07-25 21:20:49 +02:00
|
|
|
case TLKey("L1toL2") => {
|
|
|
|
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
|
2015-10-14 08:44:05 +02:00
|
|
|
TileLinkParameters(
|
2016-07-25 21:20:49 +02:00
|
|
|
coherencePolicy = (
|
|
|
|
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
|
|
|
|
else new MESICoherence(site(L2DirectoryRepresentation))),
|
2016-06-23 09:17:29 +02:00
|
|
|
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
|
2016-06-14 01:24:01 +02:00
|
|
|
nCachingClients = site(NCachedTileLinkPorts),
|
2016-07-05 21:43:33 +02:00
|
|
|
nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
|
2016-03-28 22:22:00 +02:00
|
|
|
maxClientXacts = max_int(
|
|
|
|
// L1 cache
|
2016-06-23 09:17:29 +02:00
|
|
|
site(NMSHRs) + 1 /* IOMSHR */,
|
2016-03-28 22:22:00 +02:00
|
|
|
// RoCC
|
2016-04-27 23:57:54 +02:00
|
|
|
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
|
2016-03-28 22:22:00 +02:00
|
|
|
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
|
2015-10-14 08:44:05 +02:00
|
|
|
maxManagerXacts = site(NAcquireTransactors) + 2,
|
2016-06-08 19:16:04 +02:00
|
|
|
dataBeats = innerDataBeats,
|
2015-10-17 04:15:47 +02:00
|
|
|
dataBits = site(CacheBlockBytes)*8)
|
2016-07-25 21:20:49 +02:00
|
|
|
}
|
2015-10-14 08:44:05 +02:00
|
|
|
case TLKey("L2toMC") =>
|
|
|
|
TileLinkParameters(
|
2016-03-31 00:57:13 +02:00
|
|
|
coherencePolicy = new MEICoherence(
|
|
|
|
new NullRepresentation(site(NBanksPerMemoryChannel))),
|
2015-10-14 08:44:05 +02:00
|
|
|
nManagers = 1,
|
|
|
|
nCachingClients = site(NBanksPerMemoryChannel),
|
|
|
|
nCachelessClients = 0,
|
|
|
|
maxClientXacts = 1,
|
|
|
|
maxClientsPerPort = site(NAcquireTransactors) + 2,
|
|
|
|
maxManagerXacts = 1,
|
2016-06-08 19:16:04 +02:00
|
|
|
dataBeats = innerDataBeats,
|
2015-10-17 04:15:47 +02:00
|
|
|
dataBits = site(CacheBlockBytes)*8)
|
2016-04-01 03:18:30 +02:00
|
|
|
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
|
|
|
|
maxClientXacts = site(NAcquireTransactors) + 2,
|
2016-04-29 01:15:31 +02:00
|
|
|
maxClientsPerPort = site(NBanksPerMemoryChannel),
|
2016-04-01 03:18:30 +02:00
|
|
|
dataBeats = site(MIFDataBeats))
|
2016-03-31 00:57:13 +02:00
|
|
|
case TLKey("L2toMMIO") => {
|
|
|
|
TileLinkParameters(
|
|
|
|
coherencePolicy = new MICoherence(
|
|
|
|
new NullRepresentation(site(NBanksPerMemoryChannel))),
|
2016-06-04 02:29:05 +02:00
|
|
|
nManagers = globalAddrMap.subMap("io").flatten.size,
|
2016-03-31 00:57:13 +02:00
|
|
|
nCachingClients = 0,
|
|
|
|
nCachelessClients = 1,
|
|
|
|
maxClientXacts = 4,
|
|
|
|
maxClientsPerPort = 1,
|
|
|
|
maxManagerXacts = 1,
|
2016-06-08 19:16:04 +02:00
|
|
|
dataBeats = innerDataBeats,
|
2016-03-31 00:57:13 +02:00
|
|
|
dataBits = site(CacheBlockBytes) * 8)
|
|
|
|
}
|
|
|
|
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
|
2014-10-06 22:43:40 +02:00
|
|
|
case NTiles => Knob("NTILES")
|
2016-07-18 23:09:10 +02:00
|
|
|
case AsyncMemChannels => false
|
2015-10-31 05:14:33 +01:00
|
|
|
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
|
2016-06-02 00:00:48 +02:00
|
|
|
case TMemoryChannels => BusType.AXI
|
2015-11-05 08:18:34 +01:00
|
|
|
case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
|
2016-04-29 01:15:31 +02:00
|
|
|
case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
|
2015-06-26 08:17:35 +02:00
|
|
|
case BankIdLSB => 0
|
2015-10-31 05:14:33 +01:00
|
|
|
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
|
2014-10-06 22:43:40 +02:00
|
|
|
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
|
2016-03-15 02:03:33 +01:00
|
|
|
case ConfigString => makeConfigString()
|
2016-04-29 01:15:31 +02:00
|
|
|
case GlobalAddrMap => globalAddrMap
|
2016-07-06 23:59:40 +02:00
|
|
|
case EnableL2Logging => false
|
2016-07-11 21:17:29 +02:00
|
|
|
case ExportGroundTestStatus => false
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2014-10-06 22:43:40 +02:00
|
|
|
}},
|
|
|
|
knobValues = {
|
2014-08-25 04:30:53 +02:00
|
|
|
case "NTILES" => 1
|
2015-11-05 08:18:34 +01:00
|
|
|
case "NBANKS_PER_MEM_CHANNEL" => 1
|
2014-08-25 04:30:53 +02:00
|
|
|
case "L1D_MSHRS" => 2
|
2015-06-26 08:17:35 +02:00
|
|
|
case "L1D_SETS" => 64
|
2014-08-25 04:30:53 +02:00
|
|
|
case "L1D_WAYS" => 4
|
2015-06-26 08:17:35 +02:00
|
|
|
case "L1I_SETS" => 64
|
|
|
|
case "L1I_WAYS" => 4
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2014-08-25 04:30:53 +02:00
|
|
|
}
|
2014-10-06 22:43:40 +02:00
|
|
|
)
|
2016-05-25 20:08:11 +02:00
|
|
|
class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
|
2014-08-28 22:07:54 +02:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class WithNCores(n: Int) extends Config(
|
|
|
|
knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
|
2015-07-07 03:21:06 +02:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class WithNBanksPerMemChannel(n: Int) extends Config(
|
|
|
|
knobValues = {
|
|
|
|
case "NBANKS_PER_MEM_CHANNEL" => n;
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2016-06-14 01:24:01 +02:00
|
|
|
})
|
|
|
|
|
|
|
|
class WithNMemoryChannels(n: Int) extends Config(
|
2016-02-18 00:23:30 +01:00
|
|
|
(pname,site,here) => pname match {
|
2016-06-14 01:24:01 +02:00
|
|
|
case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2016-02-18 00:23:30 +01:00
|
|
|
}
|
|
|
|
)
|
2015-10-31 08:00:09 +01:00
|
|
|
|
2015-10-22 03:23:58 +02:00
|
|
|
class WithL2Cache extends Config(
|
2015-06-26 08:17:35 +02:00
|
|
|
(pname,site,here) => pname match {
|
|
|
|
case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
|
|
|
|
case "L2Bank" => {
|
|
|
|
case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
|
|
|
|
site(CacheBlockBytes)) /
|
2015-11-05 07:15:47 +01:00
|
|
|
(site(NBanksPerMemoryChannel)*site(NMemoryChannels))) /
|
2015-06-26 08:17:35 +02:00
|
|
|
site(NWays)
|
|
|
|
case NWays => Knob("L2_WAYS")
|
2015-10-21 03:56:22 +02:00
|
|
|
case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
|
2015-11-22 01:11:22 +01:00
|
|
|
case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
|
2016-02-29 23:49:18 +01:00
|
|
|
case SplitMetadata => Knob("L2_SPLIT_METADATA")
|
2015-06-26 08:17:35 +02:00
|
|
|
}: PartialFunction[Any,Any]
|
2015-11-12 02:10:58 +01:00
|
|
|
case NAcquireTransactors => 2
|
2015-06-26 08:17:35 +02:00
|
|
|
case NSecondaryMisses => 4
|
2015-10-14 08:44:05 +02:00
|
|
|
case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
|
2015-11-22 01:11:22 +01:00
|
|
|
case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
|
2015-10-06 19:47:38 +02:00
|
|
|
Module(new L2HellaCacheBank()(p.alterPartial({
|
2015-11-22 01:11:22 +01:00
|
|
|
case CacheId => id
|
|
|
|
case CacheName => "L2Bank"
|
|
|
|
case InnerTLId => "L1toL2"
|
|
|
|
case OuterTLId => "L2toMC"})))
|
2015-12-16 19:24:57 +01:00
|
|
|
case L2Replacer => () => new SeqRandom(site(NWays))
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2015-06-26 08:17:35 +02:00
|
|
|
},
|
2016-06-08 01:13:01 +02:00
|
|
|
knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
|
2015-06-26 08:17:35 +02:00
|
|
|
)
|
|
|
|
|
2016-07-05 02:07:58 +02:00
|
|
|
class WithBufferlessBroadcastHub extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
|
|
|
|
Module(new BufferlessBroadcastHub()(p.alterPartial({
|
|
|
|
case InnerTLId => "L1toL2"
|
|
|
|
case OuterTLId => "L2toMC" })))
|
|
|
|
})
|
|
|
|
|
2016-07-22 03:33:46 +02:00
|
|
|
/**
|
|
|
|
* WARNING!!! IGNORE AT YOUR OWN PERIL!!!
|
|
|
|
*
|
|
|
|
* There is a very restrictive set of conditions under which the stateless
|
|
|
|
* bridge will function properly. There can only be a single tile. This tile
|
|
|
|
* MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
|
|
|
|
* uncached channel capable of writes (i.e. a RoCC accelerator).
|
|
|
|
*
|
|
|
|
* This is because the stateless bridge CANNOT generate probes, so if your
|
|
|
|
* system depends on coherence between channels in any way,
|
|
|
|
* DO NOT use this configuration.
|
|
|
|
*/
|
2016-07-18 23:12:22 +02:00
|
|
|
class WithStatelessBridge extends Config (
|
2016-07-22 03:33:46 +02:00
|
|
|
topDefinitions = (pname, site, here) => pname match {
|
2016-07-18 23:12:22 +02:00
|
|
|
case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
|
|
|
|
Module(new ManagerToClientStatelessBridge()(p.alterPartial({
|
|
|
|
case InnerTLId => "L1toL2"
|
|
|
|
case OuterTLId => "L2toMC" })))
|
2016-07-22 03:33:46 +02:00
|
|
|
},
|
|
|
|
knobValues = {
|
|
|
|
case "L1D_MSHRS" => 0
|
|
|
|
case _ => throw new CDEMatchError
|
2016-07-18 23:12:22 +02:00
|
|
|
}
|
|
|
|
)
|
|
|
|
|
2015-12-16 19:24:57 +01:00
|
|
|
class WithPLRU extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2015-12-16 19:24:57 +01:00
|
|
|
})
|
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class WithL2Capacity(size_kb: Int) extends Config(
|
|
|
|
knobValues = {
|
|
|
|
case "L2_CAPACITY_IN_KB" => size_kb
|
|
|
|
case _ => throw new CDEMatchError
|
|
|
|
})
|
2015-07-07 03:21:06 +02:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class WithNL2Ways(n: Int) extends Config(
|
|
|
|
knobValues = {
|
|
|
|
case "L2_WAYS" => n
|
|
|
|
case _ => throw new CDEMatchError
|
|
|
|
})
|
2015-11-21 08:26:28 +01:00
|
|
|
|
2016-05-25 20:08:11 +02:00
|
|
|
class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
|
2016-06-14 01:24:01 +02:00
|
|
|
class DefaultL2FPGAConfig extends Config(
|
|
|
|
new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
|
2015-06-26 08:17:35 +02:00
|
|
|
|
2016-07-05 02:07:58 +02:00
|
|
|
class DefaultBufferlessConfig extends Config(
|
|
|
|
new WithBufferlessBroadcastHub ++ new BaseConfig)
|
|
|
|
|
2015-12-16 19:24:57 +01:00
|
|
|
class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
|
|
|
|
|
2016-03-11 02:40:21 +01:00
|
|
|
class WithRV32 extends Config(
|
|
|
|
(pname,site,here) => pname match {
|
|
|
|
case XLen => 32
|
2016-04-02 01:41:48 +02:00
|
|
|
case UseVM => false
|
2016-05-26 00:40:53 +02:00
|
|
|
case UseUser => false
|
2016-05-25 20:08:11 +02:00
|
|
|
case UseAtomics => false
|
2016-03-11 02:40:21 +01:00
|
|
|
case UseFPU => false
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2016-03-11 02:40:21 +01:00
|
|
|
}
|
|
|
|
)
|
|
|
|
|
2015-10-22 03:23:58 +02:00
|
|
|
class FPGAConfig extends Config (
|
2014-10-06 22:43:40 +02:00
|
|
|
(pname,site,here) => pname match {
|
2015-07-31 01:30:00 +02:00
|
|
|
case NAcquireTransactors => 4
|
2016-07-11 21:17:29 +02:00
|
|
|
case ExportGroundTestStatus => true
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2014-09-24 02:05:14 +02:00
|
|
|
}
|
2014-10-06 22:43:40 +02:00
|
|
|
)
|
2014-09-24 02:05:14 +02:00
|
|
|
|
2016-05-25 20:08:11 +02:00
|
|
|
class WithBlockingL1 extends Config (
|
|
|
|
knobValues = {
|
|
|
|
case "L1D_MSHRS" => 0
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2016-05-25 20:08:11 +02:00
|
|
|
}
|
|
|
|
)
|
|
|
|
|
2016-06-02 01:18:42 +02:00
|
|
|
class WithAHB extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case TMemoryChannels => BusType.AHB
|
|
|
|
case NExtMMIOAHBChannels => 1
|
|
|
|
})
|
|
|
|
|
2016-07-01 03:20:43 +02:00
|
|
|
class WithTL extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case TMemoryChannels => BusType.TL
|
|
|
|
case NExtMMIOTLChannels => 1
|
|
|
|
})
|
|
|
|
|
2016-05-25 20:08:11 +02:00
|
|
|
class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
|
2014-09-24 02:05:14 +02:00
|
|
|
|
2016-06-23 01:08:27 +02:00
|
|
|
class WithSmallCores extends Config (
|
2014-10-06 22:43:40 +02:00
|
|
|
topDefinitions = { (pname,site,here) => pname match {
|
2015-10-21 00:04:39 +02:00
|
|
|
case UseFPU => false
|
2016-07-16 00:40:17 +02:00
|
|
|
case MulUnroll => 1
|
2016-07-15 23:40:37 +02:00
|
|
|
case DivEarlyOut => false
|
2015-06-26 08:17:35 +02:00
|
|
|
case NTLBEntries => 4
|
2016-04-02 01:41:48 +02:00
|
|
|
case BtbKey => BtbParameters(nEntries = 0)
|
2016-03-25 22:18:24 +01:00
|
|
|
case StoreDataQueueDepth => 2
|
|
|
|
case ReplayQueueDepth => 2
|
|
|
|
case NAcquireTransactors => 2
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2014-10-06 22:43:40 +02:00
|
|
|
}},
|
|
|
|
knobValues = {
|
2014-08-28 22:07:54 +02:00
|
|
|
case "L1D_SETS" => 64
|
|
|
|
case "L1D_WAYS" => 1
|
2014-10-06 22:43:40 +02:00
|
|
|
case "L1I_SETS" => 64
|
|
|
|
case "L1I_WAYS" => 1
|
2016-05-25 20:08:11 +02:00
|
|
|
case "L1D_MSHRS" => 0
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2014-08-28 22:07:54 +02:00
|
|
|
}
|
2014-10-06 22:43:40 +02:00
|
|
|
)
|
2014-08-23 10:26:03 +02:00
|
|
|
|
2016-06-23 01:08:27 +02:00
|
|
|
class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
|
|
|
|
class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
|
|
|
|
class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultSmallConfig)
|
2015-08-06 21:51:18 +02:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class DualBankConfig extends Config(
|
|
|
|
new WithNBanksPerMemChannel(2) ++ new BaseConfig)
|
2015-11-19 02:07:01 +01:00
|
|
|
class DualBankL2Config extends Config(
|
2016-06-14 01:24:01 +02:00
|
|
|
new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
|
2015-11-03 05:10:10 +01:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
|
2015-11-19 02:07:01 +01:00
|
|
|
class DualChannelL2Config extends Config(
|
2016-06-14 01:24:01 +02:00
|
|
|
new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
|
2015-11-19 02:07:01 +01:00
|
|
|
|
|
|
|
class DualChannelDualBankConfig extends Config(
|
2016-06-14 01:24:01 +02:00
|
|
|
new WithNMemoryChannels(2) ++
|
|
|
|
new WithNBanksPerMemChannel(2) ++ new BaseConfig)
|
2015-11-19 02:07:01 +01:00
|
|
|
class DualChannelDualBankL2Config extends Config(
|
2016-06-14 01:24:01 +02:00
|
|
|
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
|
2016-05-25 20:08:11 +02:00
|
|
|
new WithL2Cache ++ new BaseConfig)
|
2015-11-19 02:07:01 +01:00
|
|
|
|
2015-11-26 01:02:54 +01:00
|
|
|
class WithRoccExample extends Config(
|
2015-11-19 02:07:01 +01:00
|
|
|
(pname, site, here) => pname match {
|
2015-11-26 01:02:54 +01:00
|
|
|
case BuildRoCC => Seq(
|
2015-12-02 02:55:07 +01:00
|
|
|
RoccParameters(
|
|
|
|
opcodes = OpcodeSet.custom0,
|
|
|
|
generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
|
|
|
|
RoccParameters(
|
|
|
|
opcodes = OpcodeSet.custom1,
|
2016-02-25 07:52:02 +01:00
|
|
|
generator = (p: Parameters) => Module(new TranslatorExample()(p)),
|
|
|
|
nPTWPorts = 1),
|
2015-12-02 02:55:07 +01:00
|
|
|
RoccParameters(
|
|
|
|
opcodes = OpcodeSet.custom2,
|
|
|
|
generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
|
|
|
|
|
2015-11-19 02:07:01 +01:00
|
|
|
case RoccMaxTaggedMemXacts => 1
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2015-11-19 02:07:01 +01:00
|
|
|
})
|
|
|
|
|
2016-05-25 20:08:11 +02:00
|
|
|
class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
|
2015-11-21 08:26:28 +01:00
|
|
|
|
2016-07-01 03:20:43 +02:00
|
|
|
class WithMIFDataBits(n: Int) extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case MIFDataBits => Dump("MIF_DATA_BITS", n)
|
|
|
|
})
|
|
|
|
|
|
|
|
class MIF128BitConfig extends Config(
|
|
|
|
new WithMIFDataBits(128) ++ new BaseConfig)
|
2016-07-02 03:13:33 +02:00
|
|
|
class MIF32BitConfig extends Config(
|
|
|
|
new WithMIFDataBits(32) ++ new BaseConfig)
|
2016-07-01 03:20:43 +02:00
|
|
|
|
2016-01-07 06:38:35 +01:00
|
|
|
class WithStreamLoopback extends Config(
|
|
|
|
(pname, site, here) => pname match {
|
|
|
|
case UseStreamLoopback => true
|
|
|
|
case StreamLoopbackSize => 128
|
|
|
|
case StreamLoopbackWidth => 64
|
2016-06-08 01:13:01 +02:00
|
|
|
case _ => throw new CDEMatchError
|
2016-01-07 06:38:35 +01:00
|
|
|
})
|
|
|
|
|
2015-11-21 08:26:28 +01:00
|
|
|
class SmallL2Config extends Config(
|
2016-06-14 01:24:01 +02:00
|
|
|
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
|
|
|
|
new WithL2Capacity(256) ++ new DefaultL2Config)
|
2016-01-07 06:38:35 +01:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
|
|
|
|
class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
|
|
|
|
class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
|
|
|
|
class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
|
2016-02-18 00:23:30 +01:00
|
|
|
|
2016-06-14 01:24:01 +02:00
|
|
|
class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
|
2016-02-26 10:33:25 +01:00
|
|
|
|
2016-06-08 01:13:01 +02:00
|
|
|
class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
|
2016-02-29 23:49:18 +01:00
|
|
|
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
|
2016-03-28 22:22:00 +02:00
|
|
|
|
2016-06-21 02:58:26 +02:00
|
|
|
class DualCoreConfig extends Config(
|
|
|
|
new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
|
2016-07-22 20:36:45 +02:00
|
|
|
|
|
|
|
class TinyConfig extends Config(
|
|
|
|
new WithRV32 ++ new WithSmallCores ++
|
|
|
|
new WithStatelessBridge ++ new BaseConfig)
|