riscv/rocket-chip
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Create seperate Mul/Div paramters instead of UseFastMulDiv

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This commit is contained in:
Megan Wachs 2016-07-15 14:40:37 -07:00
parent ba08255450
commit 4c26a6bc96
2 changed files with 5 additions and 3 deletions
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2
rocket

@ -1 +1 @@
Subproject commit d91be2b545ea0eb704bf3c2b02b5d200f27426fa
Subproject commit c521632f6415cc703fdd8212f157f8ac9810d352

6
src/main/scala/Configs.scala
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@ -195,7 +195,8 @@ class BaseConfig extends Config (
case UsePerfCounters => true
case FastLoadWord => true
case FastLoadByte => false
case FastMulDiv => true
case MulDivUnroll => 8
case DivEarlyOut => true
case XLen => 64
case UseFPU => {
val env = if(site(UseVM)) List("p","v") else List("p")
@ -444,7 +445,8 @@ class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
class WithSmallCores extends Config (
topDefinitions = { (pname,site,here) => pname match {
case UseFPU => false
case FastMulDiv => false
case MulDivUnroll => 1
case DivEarlyOut => false
case NTLBEntries => 4
case BtbKey => BtbParameters(nEntries = 0)
case StoreDataQueueDepth => 2