riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add buffering and locking to TL -> AXI converter

Browse Source
This commit is contained in:
Howard Mao 2016-07-06 16:54:58 -07:00
parent e27cb5f885
commit 8c13e78ab5
4 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
groundtest

@ -1 +1 @@
Subproject commit 4ecc9ec310bddb6841f71c7c2887e5c4bec1a297
Subproject commit a7c8c20300c1218b9d8f56c6f3d62f46b0359648

2
junctions

@ -1 +1 @@
Subproject commit 4c04c27df802ae94c7a54ac24ab792dac9651b99
Subproject commit 46db745fe3806733257a16766dd97a281810c6d5

2
src/main/scala/Configs.scala
View File

@ -8,6 +8,7 @@ import uncore.tilelink._
import uncore.coherence._
import uncore.agents._
import uncore.devices._
import uncore.converters._
import rocket._
import rocket.Util._
import groundtest._
@ -307,6 +308,7 @@ class BaseConfig extends Config (
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case EnableL2Logging => false
case NastiResponseBufferDepth => site(MIFDataBeats) * site(NAcquireTransactors)
case _ => throw new CDEMatchError
}},
knobValues = {

2
uncore

@ -1 +1 @@
Subproject commit 8d28d89b18b24cf3b354fab8fc5173344bc546f7
Subproject commit 2109a48e18719383942d535ff4c1d0a859dcc424