riscv/rocket-chip
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add PLRU replacement option to L2 cache

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This commit is contained in:
Howard Mao 2015-12-16 10:24:57 -08:00
parent 7ad9deeaee
commit 560fdc19a8
2 changed files with 9 additions and 1 deletions
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8
src/main/scala/Configs.scala
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@ -261,10 +261,16 @@ class WithL2Cache extends Config(
case CacheName => "L2Bank"
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMC"})))
case L2Replacer => () => new SeqRandom(site(NWays))
},
knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
)
class WithPLRU extends Config(
(pname, site, here) => pname match {
case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
})
class WithL2Capacity2048 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 2048 })
class WithL2Capacity1024 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 1024 })
class WithL2Capacity512 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 512 })
@ -281,6 +287,8 @@ class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfi
class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig)
class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
class WithZscale extends Config(
(pname,site,here) => pname match {
case XLen => 32

2
uncore

@ -1 +1 @@
Subproject commit ab8a6614f5495ee97c5b8bb82047ebb24cb20d7c
Subproject commit f9eda0ebb010a4bf99609d2ef6f93b85756e3ccb