riscv/rocket-chip
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  • 5e2f98747f Merge branch 'dse' Henry Cook 2014-09-06 06:10:15 -0700
  • 1cb2d1d7b7 initialize all SRAMs to avoid X propagation problem Yunsup Lee 2014-09-04 11:06:01 -0700
  • 763c57931b fix problem introduced with verilog generation in vsim/fsim Yunsup Lee 2014-09-04 09:49:57 -0700
  • 6c6f5a3843 add verilog target to build without simulator Scott Beamer 2014-09-03 17:28:45 -0700
  • 13b6ec4712 including better sbt fixes Scott Beamer 2014-09-02 15:16:31 -0700
  • f8821b4cc9 better fix with explanation of sbt issue Scott Beamer 2014-09-02 15:16:03 -0700
  • 600c5d50a9 better fix with explanation of sbt issue Scott Beamer 2014-09-02 15:14:56 -0700
  • 26649b30ed fixes sbt error during first run Scott Beamer 2014-09-02 14:34:55 -0700
  • f9922a106b fixes sbt error during first run Scott Beamer 2014-09-02 14:34:36 -0700
  • bfb662968d fixes sbt error during first run Scott Beamer 2014-09-02 14:33:58 -0700
  • 82467313dd merge in rocketchip changes from master Henry Cook 2014-09-02 13:51:57 -0700
  • 3250db0dd5 bump uncore Henry Cook 2014-09-02 12:37:44 -0700
  • 712f3a754d merge in master Henry Cook 2014-09-02 12:34:42 -0700
  • 8622eb0f5b bump rocket Henry Cook 2014-09-01 13:34:15 -0700
  • b42a2ab40a Final parameter refactor Henry Cook 2014-09-01 13:28:58 -0700
  • 2d6aafc32e Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD Adam Izraelevitz 2014-09-01 11:23:50 -0700
  • 7734285507 forgot to comment out hwacha Yunsup Lee 2014-09-01 09:01:36 -0700
  • 0d18e491c7 update gitignore Yunsup Lee 2014-09-01 08:59:59 -0700
  • 882fecf43a update README Yunsup Lee 2014-08-31 20:57:16 -0700
  • c03c09ec31 update for rocket-chip release Yunsup Lee 2014-08-31 20:26:55 -0700
  • 83c6c2c9e2 rename refs to zynq-fpga to fpga-zynq Sagar Karandikar 2014-08-29 10:26:48 -0700
  • 78ab83d224 refactor fpga top/config Henry Cook 2014-08-28 13:07:54 -0700
  • 83380053de use fpga backend for fpga Scott Beamer 2014-08-26 15:56:27 -0700
  • bf356b9cb4 Refactor to combine fpga and vlsi tops, part 1 Henry Cook 2014-08-24 19:30:53 -0700
  • 17b2359c9a htif parameters trait Henry Cook 2014-08-24 19:27:58 -0700
  • a41d55b643 Final parameter refactor. Henry Cook 2014-08-23 01:26:03 -0700
  • dc5643b12f Final parameter refactor. Henry Cook 2014-08-23 01:19:36 -0700
  • 63b62394d9 added l2 to fpga with new chisel & uncore, it goes into brams Scott Beamer 2014-08-20 15:41:07 -0700
  • e384b33cc3 don't generate a write mask for BigMem if it isn't used not needed for llc data Scott Beamer 2014-08-19 15:50:20 -0700
  • 9b36162b67 Point rocket/ to rocket-staging repo Henry Cook 2014-08-19 14:20:15 -0700
  • 2741bbf2b9 Point rocket/ to rocket-staging repo Henry Cook 2014-08-19 13:53:24 -0700
  • 6a4193cf90 minor cache param cleanup Henry Cook 2014-08-14 11:31:42 -0700
  • 2de268b3b1 Cache utility traits. Completely compiles, asm tests hang. Henry Cook 2014-08-11 18:36:23 -0700
  • ca5f38ff26 a few more fixes. some param lookups fail (here() in Alter blocks) Henry Cook 2014-08-10 23:07:15 -0700
  • 0dac9a7467 Full conversion to params. Compiles but does not elaborate. Henry Cook 2014-08-08 12:23:02 -0700
  • 4e6d69892d Added initial brainstorm for parameter hierarchical flattening, does not compile ;) Adam Izraelevitz 2014-08-04 14:06:52 -0700
  • 812353bace Ported FPU parameters to new Chisel Parameters Adam Izraelevitz 2014-08-01 18:01:08 -0700
  • 4ac8e59b1f add .gitignore Yunsup Lee 2014-08-18 19:27:50 -0700
  • d520846638 add README and sbt files Yunsup Lee 2014-08-18 19:23:10 -0700
  • e1a4d12c65 fix small typos in README Scott Beamer 2014-08-14 17:59:24 -0700
  • 1563c1bb36 Fixed cache params. Asm and bmark tests pass. Henry Cook 2014-08-12 15:00:54 -0700
  • e26f8a6f6a Fix errors in derived cache params Henry Cook 2014-08-12 14:55:44 -0700
  • 910c886837 bump chisel Henry Cook 2014-08-12 14:53:19 -0700
  • 74796868e7 chisel bump Henry Cook 2014-08-12 10:58:09 -0700
  • 0ca24a5d91 fix debug flags Henry Cook 2014-08-12 10:35:39 -0700
  • 7f07771600 Cache utility traits. Completely compiles, asm tests hang. Henry Cook 2014-08-11 18:37:10 -0700
  • 9ab3a4262c Cache utility traits. Completely compiles, asm tests hang. Henry Cook 2014-08-11 18:35:49 -0700
  • 1983260e6f a few more fixes. some param lookups fail (here() in Alter blocks) Henry Cook 2014-08-10 23:08:21 -0700
  • 63bd0b9d2a Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. Henry Cook 2014-08-08 12:27:47 -0700
  • f411fdcce3 Full conversion to params. Compiles but does not elaborate. Henry Cook 2014-08-08 12:21:57 -0700
  • d3a8a224fe README updated for new fpga flow Scott Beamer 2014-08-07 14:52:56 -0700
  • e390eba8ce convert README to markdown Scott Beamer 2014-08-07 14:50:31 -0700
  • 4109d7cc87 newest version of chisel needed for brams Scott Beamer 2014-08-07 13:49:31 -0700
  • 0fc3acb978 Update the directions on how to update Chisel Palmer Dabbelt 2014-08-05 11:56:03 -0700
  • 693489da87 Add a note to the README about "make emulator-debug" Palmer Dabbelt 2014-08-05 11:53:55 -0700
  • 08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu Adam Izraelevitz 2014-08-01 18:09:37 -0700
  • fcd68364ff Merge branch 'master' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-08-01 18:07:22 -0700
  • 7bffc6c586 rename Unsigned.size to Unsigned.clog2 Andrew Waterman 2014-06-06 16:59:55 -0700
  • 3828c628c3 Remove vestigial control signals Andrew Waterman 2014-06-03 10:28:42 -0700
  • 04593d433e clean up Int <-> Boolean conversion stuff Andrew Waterman 2014-05-25 23:59:24 -0700
  • ac88ded35a Use ROMs to reduce node count and improve QoR a bit Andrew Waterman 2014-05-25 23:58:53 -0700
  • 88899eafe0 Reduce node count a bit Andrew Waterman 2014-05-25 23:58:25 -0700
  • 0c93567dea Replace needWidth() with getWidth. Jim Lawson 2014-06-13 14:58:52 -0700
  • 0020ded367 Replace needWidth() with getWidth. Jim Lawson 2014-06-13 14:53:48 -0700
  • de32595fba Quick change to work with new Width class. Jim Lawson 2014-06-13 12:00:50 -0700
  • a04ef4f5f4 Quick change to work with new Width class. Jim Lawson 2014-06-13 11:44:43 -0700
  • 1ae7a9376c Fix unhandled LLC writeback hazard Andrew Waterman 2014-06-13 03:25:52 -0700
  • 434da22283 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) Henry Cook 2014-05-28 14:45:41 -0700
  • dab675b231 refactor Metadata, clean and expand coherence API Henry Cook 2014-05-28 13:30:48 -0700
  • b0ccb88982 make outer cache type choice a top-level const Henry Cook 2014-05-06 13:11:41 -0700
  • 3c329df7e7 refactor Metadata, clean and expand coherence API Henry Cook 2014-05-28 13:35:08 -0700
  • 8bc1c33540 Fix BTB error (requires Chisel update) Andrew Waterman 2014-05-19 18:56:30 -0700
  • 364a6de214 Use Mem instead of Vec[Reg] Andrew Waterman 2014-05-18 19:26:35 -0700
  • cbb37ccc3e Use Mem instead of Vec[Reg] Andrew Waterman 2014-05-18 19:25:43 -0700
  • e91e12ed88 Fix RoCC accumulator example Andrew Waterman 2014-05-14 16:17:39 -0700
  • 4ca152b012 Use BundleWithConf to avoid clone method boilerplate Andrew Waterman 2014-05-09 19:30:05 -0700
  • 94c1f01ec6 Deanonymize CSRFile's IO bundle Andrew Waterman 2014-05-09 19:26:43 -0700
  • fd5f419eb1 use getWidth instead of width Andrew Waterman 2014-05-09 19:10:14 -0700
  • 0c13c00d08 Reduce node count by avoiding elsewhen :-( Andrew Waterman 2014-05-09 19:09:26 -0700
  • 8dcc0cbb53 Fix bug with multiple DecodeLogics per module Andrew Waterman 2014-05-04 20:02:31 -0700
  • 0e39346a12 L2-specific metadataarray wrapper, hookups to tshrfile Henry Cook 2014-05-07 01:51:46 -0700
  • 5bc6981414 fix metadata default, add bug TODO Henry Cook 2014-05-06 18:36:22 -0700
  • d2a3b1dc20 Merge branch 'shapeanalysis' Stephen Twigg 2014-05-06 16:49:54 -0700
  • f8b3117ac0 bump rocket, uncore Henry Cook 2014-05-06 13:10:12 -0700
  • 7d6a642c0c correct use of function value to initialize MetaDataArray Henry Cook 2014-05-06 13:00:00 -0700
  • bc3ef1011e correct use of function value to initialize MetaDataArray Henry Cook 2014-05-06 12:59:45 -0700
  • 445d4f2eee bump rocket, uncore Henry Cook 2014-05-01 01:46:55 -0700
  • 7f690dd9c8 parameterize metadataarray Henry Cook 2014-05-01 01:45:45 -0700
  • 45172f1f37 parameterize metadataarray Henry Cook 2014-05-01 01:44:59 -0700
  • ce056b4b89 client/master -> inner/outer Henry Cook 2014-04-29 16:50:07 -0700
  • 0237229921 client/master -> inner/outer Henry Cook 2014-04-29 16:49:18 -0700
  • 224e286dd3 New uncore config objects. Backends get their own file. Simplify fpga uncore. Henry Cook 2014-04-26 19:16:37 -0700
  • 52c6de5641 DRAMSideLLCLike trait. TSHRFile. New L2 config objects. Henry Cook 2014-04-26 19:11:36 -0700
  • 519b2ea2b6 New metadata result trait Henry Cook 2014-04-26 19:08:56 -0700
  • 3d4273954a TileLinkIO.GrantAck -> TileLinkIO.Finish Henry Cook 2014-04-26 15:19:25 -0700
  • 1b156c6db9 TileLinkIO.GrantAck -> TileLinkIO.Finish Henry Cook 2014-04-26 15:18:21 -0700
  • 1163131d1e TileLinkIO.GrantAck -> TileLinkIO.Finish Henry Cook 2014-04-26 15:17:05 -0700
  • 3f53d532c2 uniquify tilelink conf val name for easier subtyping Henry Cook 2014-04-26 14:58:38 -0700
  • fbf6e44376 fix connection error in fpga uncore Henry Cook 2014-04-24 11:58:59 -0700
  • 1e062d1bcd bump rocket, uncore Henry Cook 2014-04-23 16:27:34 -0700