Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
This commit is contained in:
Henry Cook
parent
08d81d0892
commit
63bd0b9d2a
2
rocket
2
rocket
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@ -1 +1 @@
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Subproject commit 1b01778c1743d779966829e0edfb904528ac472f
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Subproject commit 6beea1debbdd8115f45d02318210df624e67e9f8
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@ -21,58 +21,196 @@ class DefaultConfig extends ChiselConfig {
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case "NL2_REL_XACTS" => 1
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case "NL2_ACQ_XACTS" => 7
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case "NMSHRS" => 2
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//FPUConstants
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case HasFPU => true
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//Coherence
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case Coherence => {
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val dir = new FullRepresentation(site[Int]("NTILES")+1)
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if(site[Boolean]("ENABLE_SHARING")) {
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if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir)
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else new MSICoherence(dir)
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} else {
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if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir)
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else new MICoherence(dir)
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}
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}
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//Rocket Constants
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// Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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// Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc
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case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case BuildRoCC => None
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case RetireWidth => 1
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case UseVM => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case DcacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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case XprLen => 64
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case NXpr => 32
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case NXprBits => log2Up(here(NXpr))
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case BuildFPU => Some(() => new FPU)
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case FPUParams => Alter({
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case SFMALatency => 2
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case DFMALatency => 3
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})
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case RocketDCacheParams => Alter({
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//L1 Specific
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => site[Int]("NMSHRS")
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case NTLBEntries => 8
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case CoreReqTagBits => site(DcacheReqTagBits)
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case CoreDataBits => site(XprLen)
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case RowWords => 2
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case ECCCode => new IdentityCode
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//From uncore/cache.scala
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case NSets => 128
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case NWays => 4
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case IsDM => here(NWays) == 1
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case OffBits => log2Up(site(TLDataBits))
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case IdxBits => log2Up(here(NSets))
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case UntagBits => here(OffBits) + here(IdxBits)
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case TagBits => here(PAddrBits) - here(UntagBits)
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case WayBits => log2Up(here(NWays))
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case Replacer => () => new RandomReplacement(site(NWays))
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case RowBits => here(RowWords)*here(CoreDataBits)
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case WordBits => here(CoreDataBits)
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case RefillCycles => site(TLDataBits)/here(RowBits)
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//Derived
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case MaxAddrBits => math.max(site(PPNBits),site(VPNBits)+1) + site(PgIdxBits)
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case CoreDataBytes => here(CoreDataBits)/8
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case WordOffBits => log2Up(here(CoreDataBytes))
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case RowBytes => here(RowWords)*here(CoreDataBytes)
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case RowOffBits => log2Up(here(RowBytes))
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case DoNarrowRead => here(CoreDataBits)*here(NWays) % here(RowBits) == 0
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case EncDataBits => here(ECCCode).width(here(CoreDataBits))
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case EncRowBits => here(RowWords)*here(EncDataBits)
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case LRSCCycles => 32
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})
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case RocketFrontendParams => Alter({
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case InstBytes => 4
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case RowBytes => 16
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case NTLBEntries => 8
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case ECCCode => new IdentityCode
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//From uncore/cache.scala
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case NSets => 128
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case NWays => 2
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case IsDM => here(NWays) == 1
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case OffBits => log2Up(site(TLDataBits)/8)
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case IdxBits => log2Up(here(NSets))
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case UntagBits => here(OffBits) + here(IdxBits)
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case TagBits => here(PAddrBits) - here(UntagBits)
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case WayBits => log2Up(here(NWays))
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case Replacer => () => new RandomReplacement(site(NWays))
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case RowBits => here(RowBytes)*8
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case RefillCycles => site(TLDataBits)/here(RowBits)
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case RowOffBits => log2Up(here(RowBytes))
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})
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case CoreBTBParams => Alter({
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case Entries => 62
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case NRAS => 2
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case MatchBits => site(PgIdxBits)
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case Pages => ((1 max(log2Up(here(Entries))))+1)/2*2
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// control logic assumes 2 divides pages
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case OpaqueBits => log2Up(here(Entries))
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case NBHT => 1 << log2Up(here(Entries)*2)
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})
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//MemoryConstants
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case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 //TODO: How configurable is this really?
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case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6
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case "OFFSET_BITS" => log2Up(here[Int]("CACHE_DATA_SIZE_IN_BYTES"))
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case "PADDR_BITS" => 32
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case "VADDR_BITS" => 43
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case "PGIDX_BITS" => 13
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case "ASID_BITS" => 7
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case "PERM_BITS" => 6
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case "MEM_TAG_BITS" => 5
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case "MEM_DATA_BITS" => 128
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case "MEM_ADDR_BITS" => here[Int]("PADDR_BITS") - here[Int]("OFFSET_BITS")
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case "MEM_DATA_BEATS" => 4
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//TileLinkSizeConstants
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case "WRITE_MASK_BITS" => 6
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case "SUBWORD_ADDR_BITS" => 3
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case "ATOMIC_OP_BITS" => 4
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => here(PAddrBits) - here(PgIdxBits)
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case VPNBits => here(VAddrBits) - here(PgIdxBits)
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case MIFTagBits => 5
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case MIFDataBits => 128
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case MIFAddrBits => here(PAddrBits) - here[Int]("OFFSET_BITS")
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case MIFDataBeats => 4
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//Uncore Constants
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case TileLinkL1Params => Alter({
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case LNMasters => site[Int]("NBANKS")
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case LNClients => site[Int]("NTILES")+1
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case LNEndpoints => here(LNMasters) + here(LNClients)
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case TLCoherence => site(Coherence)
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case TLAddrBits => site[Int]("PADDR_BITS") - site[Int]("OFFSET_BITS")
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case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS"))
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case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1)
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case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8
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case TLWriteMaskBits => 6
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case TLWordAddrBits => 3
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case TLAtomicOpBits => 4
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})
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case L2HellaCacheParams => Alter({
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case NReleaseTransactors => site[Int]("NL2_REL_XACTS")
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case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS")
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case NTransactors => here(NReleaseTransactors) + here(NAcquireTransactors)
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case NClients => site[Int]("NTILES") + 1
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case NSets => 512
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case NWays => 8
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case IsDM => here(NWays) == 1
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case OffBits => 0
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case IdxBits => log2Up(here(NSets))
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case UntagBits => here(OffBits) + here(IdxBits)
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case TagBits => here(PAddrBits) - here(UntagBits)
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case WayBits => log2Up(here(NWays))
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case Replacer => () => new RandomReplacement(site(NWays))
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case RowBits => site(TLDataBits)
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case WordBits => 64
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case RefillCycles => site(TLDataBits)/here(RowBits)
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})
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case NTiles => here[Int]("NTILES")
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case NBanks => here[Int]("NBANKS")
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case BankIdLSB => 5
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case BuildDRAMSideLLC => () => {
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val refill = site(TLDataBits)/site(MIFDataBits)
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if(site[Boolean]("USE_DRAMSIDE_LLC")) {
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val tag = Mem(Bits(width = 152), 512, seqRead = true)
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val data = Mem(Bits(width = 64), 4096, seqRead = true)
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Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
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refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
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} else { Module(new DRAMSideLLCNull(16, refill)) }
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}
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case BuildCoherentMaster => (id: Int) => {
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if(!site[Boolean]("USE_DRAMSIDE_LLC")) {
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Module(new L2CoherenceAgent(id), here(L2HellaCacheParams))
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} else {
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Module(new L2HellaCache(id), here(L2HellaCacheParams))
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}
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}
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//HTIF Constants
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case HTIFWidth => 16
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case HTIFNSCR => 64
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case HTIFOffsetBits => here[Int]("OFFSET_BITS")
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case HTIFNCores => here[Int]("NTILES")
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}
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}
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}
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case object NTiles extends Field[Int]
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case object NBanks extends Field[Int]
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case object BankIdLSB extends Field[Int]
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case object TileLinkL1Params extends Field[PF]
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case object L2HellaCacheParams extends Field[PF]
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case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike]
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case object BuildCoherentMaster extends Field[Int => CoherenceAgent]
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case object Coherence extends Field[CoherencePolicyWithUncached]
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class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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class OuterMemorySystem extends Module
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{
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implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif)
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val io = new Bundle {
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
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val htif = (new TileLinkIO).flip
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput
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val mem = new MemIO
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val mem_backup = new MemSerializedIO(htif_width)
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val mem_backup = new MemSerializedIO(params(HTIFWidth))
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val mem_backup_en = Bool(INPUT)
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}
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val refill_cycles = tl.dataBits/mif.dataBits
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val (llc, masterEndpoints) = if(conf.useDRAMSideLLC) {
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val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
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val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
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val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
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refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
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val mes = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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(llc, mes)
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} else {
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val llc = Module(new DRAMSideLLCNull(16, refill_cycles))
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val mes = (0 until ln.nMasters).map(i => Module(new L2HellaCache(i)))
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(llc, mes)
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}
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val refill_cycles = params(TLDataBits)/params(MIFDataBits)
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val llc = params(BuildDRAMSideLLC)()
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val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster))
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val net = Module(new ReferenceChipCrossbarNetwork)
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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@ -80,8 +218,8 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
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if(ln.nMasters > 1) {
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
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if(params(NBanks) > 1) {
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)))
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arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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} else {
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@ -92,7 +230,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
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conv.io.mem.resp <> llc.io.cpu.resp
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// mux between main and backup memory ports
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val mem_serdes = Module(new MemSerdes(htif_width))
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val mem_serdes = Module(new MemSerdes(params(HTIFWidth)))
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val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
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mem_cmdq.io.enq <> llc.io.mem.req_cmd
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mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
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@ -116,22 +254,22 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
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io.mem_backup <> mem_serdes.io.narrow
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}
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case class UncoreConfiguration(l2: L2CacheConfig, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int, useDRAMSideLLC: Boolean)
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class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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class Uncore extends Module
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{
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implicit val (tl, mif) = (conf.tl, conf.mif)
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require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
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val htif_width = params(HTIFWidth)
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val io = new Bundle {
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val host = new HostIO(htif_width)
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val mem = new MemIO
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
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val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
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val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
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val htif = Vec.fill(params(NTiles)){new HTIFIO}.flip
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val incoherent = Vec.fill(params(NTiles)){Bool()}.asInput
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val mem_backup = new MemSerializedIO(htif_width)
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val mem_backup_en = Bool(INPUT)
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}
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val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits))
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val outmemsys = Module(new OuterMemorySystem(htif_width))
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val htif = Module(new HTIF(CSRs.reset))
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val outmemsys = Module(new OuterMemorySystem)
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val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
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outmemsys.io.incoherent := incoherentWithHtif
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htif.io.cpu <> io.htif
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@ -140,21 +278,20 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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// Add networking headers and endpoint queues
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def convertAddrToBank(addr: Bits): UInt = {
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require(conf.bankIdLsb + log2Up(conf.nBanks) < conf.mif.addrBits, {println("Invalid bits for bank multiplexing.")})
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addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
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addr(params(BankIdLSB) + log2Up(params(NBanks)) - 1, params(BankIdLSB))
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}
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(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
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case ((outer, client), i) =>
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, params(NBanks), convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, params(NBanks), convertAddrToBank _))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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}
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// pad out the HTIF using a divided clock
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val hio = Module((new SlowIO(512)) { Bits(width = htif_width+1) })
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val hio = Module((new SlowIO(512)) { Bits(width = params(HTIFWidth)+1) })
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hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
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hio.io.set_divisor.bits := htif.io.scr.wdata
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htif.io.scr.rdata(63) := hio.io.divisor
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@ -183,12 +320,12 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
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}
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class TopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends Bundle {
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val host = new HostIO(htifWidth)
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class TopIO extends Bundle {
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val host = new HostIO(params(HTIFWidth))
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val mem = new MemIO
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}
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class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) {
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class VLSITopIO extends TopIO {
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val mem_backup_en = Bool(INPUT)
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val in_mem_ready = Bool(OUTPUT)
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val in_mem_valid = Bool(INPUT)
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@ -196,58 +333,27 @@ class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends To
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val out_mem_valid = Bool(OUTPUT)
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}
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class MemDessert extends Module {
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implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS"))
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val io = new MemDesserIO(params[Int]("HTIF_WIDTH"))
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val x = Module(new MemDesser(params[Int]("HTIF_WIDTH")))
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val io = new MemDesserIO(params(HTIFWidth))
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val x = Module(new MemDesser(params(HTIFWidth)))
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io.narrow <> x.io.narrow
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io.wide <> x.io.wide
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}
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class Top extends Module {
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val dir = new FullRepresentation(params[Int]("NTILES")+1)
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val co = if(params[Boolean]("ENABLE_SHARING")) {
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if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir)
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else new MSICoherence(dir)
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} else {
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if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir)
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else new MICoherence(dir)
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}
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implicit val ln = LogicalNetworkConfiguration(log2Up(params[Int]("NTILES"))+1, params[Int]("NBANKS"), params[Int]("NTILES")+1)
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||||
implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS"))
|
||||
implicit val tl = TileLinkConfiguration(co = co, ln = ln,
|
||||
addrBits = as.paddrBits-params[Int]("OFFSET_BITS"),
|
||||
clientXactIdBits = log2Up(params[Int]("NL2_REL_XACTS")+params[Int]("NL2_ACQ_XACTS")),
|
||||
masterXactIdBits = 2*log2Up(params[Int]("NMSHRS")*params[Int]("NTILES")+1),
|
||||
dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8,
|
||||
writeMaskBits = params[Int]("WRITE_MASK_BITS"),
|
||||
wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"),
|
||||
atomicOpBits = params[Int]("ATOMIC_OP_BITS"))
|
||||
implicit val l2 = L2CacheConfig(512, 8, 1, 1, params[Int]("NL2_REL_XACTS"), params[Int]("NL2_ACQ_XACTS"), tl, as)
|
||||
implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS"))
|
||||
implicit val uc = UncoreConfiguration(l2, tl, mif, params[Int]("NTILES"), params[Int]("NBANKS"), bankIdLsb = 5, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"), useDRAMSideLLC = params[Boolean]("USE_DRAMSIDE_LLC"))
|
||||
//val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
|
||||
//val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
|
||||
|
||||
val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2))
|
||||
val dc = DCacheConfig(sets = 128, ways = 4,
|
||||
tl = tl, as = as,
|
||||
ntlb = 8, nmshr = params[Int]("NMSHRS"), nrpq = 16, nsdq = 17,
|
||||
reqtagbits = -1, databits = -1)
|
||||
val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
|
||||
val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
|
||||
val rc = RocketConfiguration(tl, as, ic, dc
|
||||
// rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
|
||||
)
|
||||
val nTiles = params(NTiles)
|
||||
val io = new VLSITopIO
|
||||
|
||||
val io = new VLSITopIO(params[Int]("HTIF_WIDTH"))
|
||||
params.alter(params(TileLinkL1Params))
|
||||
val resetSigs = Vec.fill(nTiles){Bool()}
|
||||
val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
|
||||
val uncore = Module(new Uncore)
|
||||
|
||||
val resetSigs = Vec.fill(uc.nTiles){Bool()}
|
||||
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
|
||||
val uncore = Module(new Uncore(params[Int]("HTIF_WIDTH")))
|
||||
|
||||
for (i <- 0 until uc.nTiles) {
|
||||
for (i <- 0 until nTiles) {
|
||||
val hl = uncore.io.htif(i)
|
||||
val tl = uncore.io.tiles(i)
|
||||
val il = uncore.io.incoherent(i)
|
||||
|
|
|
|||
|
|
@ -6,17 +6,15 @@ import rocket._
|
|||
import DRAMModel._
|
||||
import DRAMModel.MemModelConstants._
|
||||
|
||||
class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
|
||||
extends Module {
|
||||
implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif)
|
||||
class FPGAOuterMemorySystem extends Module {
|
||||
val io = new Bundle {
|
||||
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
|
||||
val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
|
||||
val htif = (new TileLinkIO).flip
|
||||
val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
|
||||
val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput
|
||||
val mem = new MemIO
|
||||
}
|
||||
|
||||
val master = Module(new L2CoherenceAgent(0))
|
||||
val master = Module(new L2CoherenceAgent(0), params(L2HellaCacheParams))
|
||||
val net = Module(new ReferenceChipCrossbarNetwork)
|
||||
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
|
||||
net.io.masters.head <> master.io.inner
|
||||
|
|
@ -25,24 +23,21 @@ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfigurat
|
|||
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
|
||||
conv.io.uncached <> master.io.outer
|
||||
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
|
||||
io.mem.req_data <> Queue(conv.io.mem.req_data, tl.dataBits/mif.dataBits)
|
||||
io.mem.req_data <> Queue(conv.io.mem.req_data, params(TLDataBits)/params(MIFDataBits))
|
||||
conv.io.mem.resp <> Queue(io.mem.resp)
|
||||
}
|
||||
|
||||
case class FPGAUncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nSCR: Int, offsetBits: Int)
|
||||
|
||||
class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
|
||||
extends Module {
|
||||
implicit val (tl, ln, mif) = (conf.tl, conf.tl.ln, conf.mif)
|
||||
class FPGAUncore extends Module {
|
||||
val (htifw, nTiles) = (params(HTIFWidth),params(NTiles))
|
||||
val io = new Bundle {
|
||||
val host = new HostIO(htif_width)
|
||||
val host = new HostIO(htifw)
|
||||
val mem = new MemIO
|
||||
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
|
||||
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
|
||||
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
|
||||
val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
|
||||
val htif = Vec.fill(nTiles){new HTIFIO}.flip
|
||||
val incoherent = Vec.fill(nTiles){Bool()}.asInput
|
||||
}
|
||||
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits))
|
||||
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width))
|
||||
val htif = Module(new HTIF(CSRs.reset))
|
||||
val outmemsys = Module(new FPGAOuterMemorySystem)
|
||||
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
|
||||
outmemsys.io.incoherent := incoherentWithHtif
|
||||
htif.io.cpu <> io.htif
|
||||
|
|
@ -62,13 +57,13 @@ class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
|
|||
htif.io.host.in <> io.host.in
|
||||
}
|
||||
|
||||
class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
|
||||
class FPGATopIO extends TopIO
|
||||
|
||||
class FPGATop extends Module {
|
||||
/*
|
||||
val ntiles = 1
|
||||
val nmshrs = 2
|
||||
val htif_width = 16
|
||||
|
||||
val co = new MESICoherence(new FullRepresentation(ntiles+1))
|
||||
implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
|
||||
implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS"))
|
||||
|
|
@ -88,14 +83,18 @@ class FPGATop extends Module {
|
|||
val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1)
|
||||
val rc = RocketConfiguration(tl, as, ic, dc,
|
||||
fastMulDiv = false)
|
||||
*/
|
||||
|
||||
val io = new FPGATopIO(htif_width)
|
||||
val nTiles = params(NTiles)
|
||||
val io = new FPGATopIO
|
||||
|
||||
val resetSigs = Vec.fill(uc.nTiles){Bool()}
|
||||
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
|
||||
val uncore = Module(new FPGAUncore(htif_width))
|
||||
params.alter(params(TileLinkL1Params))
|
||||
|
||||
for (i <- 0 until uc.nTiles) {
|
||||
val resetSigs = Vec.fill(nTiles){Bool()}
|
||||
val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
|
||||
val uncore = Module(new FPGAUncore)
|
||||
|
||||
for (i <- 0 until nTiles) {
|
||||
val hl = uncore.io.htif(i)
|
||||
val tl = uncore.io.tiles(i)
|
||||
val il = uncore.io.incoherent(i)
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ import scala.reflect._
|
|||
import scala.reflect.runtime.universe._
|
||||
|
||||
object TileLinkHeaderOverwriter {
|
||||
def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
val out = in.clone.asDirectionless
|
||||
out.bits.payload := in.bits.payload
|
||||
out.bits.header.src := UInt(clientId)
|
||||
|
|
@ -15,29 +15,26 @@ object TileLinkHeaderOverwriter {
|
|||
in.ready := out.ready
|
||||
out
|
||||
}
|
||||
def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false)
|
||||
out.bits.header.dst := (if(nBanks > 1) addrConvert(in.bits.payload.addr) else UInt(0))
|
||||
out
|
||||
}
|
||||
}
|
||||
|
||||
class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
|
||||
extends LogicalNetwork[TileLinkIO]()(conf.ln) {
|
||||
implicit val (ln, co) = (conf.ln, conf.co)
|
||||
class ReferenceChipCrossbarNetwork extends LogicalNetwork {
|
||||
val io = new Bundle {
|
||||
val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip}
|
||||
val masters = Vec.fill(ln.nMasters){new TileLinkIO}
|
||||
val clients = Vec.fill(params(LNClients)){(new TileLinkIO).flip}
|
||||
val masters = Vec.fill(params(LNMasters)){new TileLinkIO}
|
||||
}
|
||||
|
||||
implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
|
||||
|
||||
val n = params(LNEndpoints)
|
||||
// Actually instantiate the particular networks required for TileLink
|
||||
val acqNet = Module(new BasicCrossbar(new Acquire))
|
||||
val relNet = Module(new BasicCrossbar(new Release))
|
||||
val prbNet = Module(new BasicCrossbar(new Probe))
|
||||
val gntNet = Module(new BasicCrossbar(new Grant))
|
||||
val ackNet = Module(new BasicCrossbar(new Finish))
|
||||
val acqNet = Module(new BasicCrossbar(n, new Acquire))
|
||||
val relNet = Module(new BasicCrossbar(n, new Release))
|
||||
val prbNet = Module(new BasicCrossbar(n, new Probe))
|
||||
val gntNet = Module(new BasicCrossbar(n, new Grant))
|
||||
val ackNet = Module(new BasicCrossbar(n, new Finish))
|
||||
|
||||
// Aliases for the various network IO bundle types
|
||||
type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
|
||||
|
|
@ -57,16 +54,16 @@ class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
|
|||
}
|
||||
def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
|
||||
val out = DefaultFromCrossbarShim(in)
|
||||
out.bits.header.src := in.bits.header.src - UInt(ln.nMasters)
|
||||
out.bits.header.src := in.bits.header.src - UInt(params(LNMasters))
|
||||
out
|
||||
}
|
||||
def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
|
||||
val out = DefaultFromCrossbarShim(in)
|
||||
out.bits.header.dst := in.bits.header.dst - UInt(ln.nMasters)
|
||||
out.bits.header.dst := in.bits.header.dst - UInt(params(LNMasters))
|
||||
out
|
||||
}
|
||||
def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
|
||||
val out = Decoupled(new PhysicalNetworkIO(in.bits.payload)).asDirectionless
|
||||
val out = Decoupled(new PhysicalNetworkIO(n,in.bits.payload)).asDirectionless
|
||||
out.bits.header := in.bits.header
|
||||
out.bits.payload := in.bits.payload
|
||||
out.valid := in.valid
|
||||
|
|
@ -75,12 +72,12 @@ class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
|
|||
}
|
||||
def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
|
||||
val out = DefaultToCrossbarShim(in)
|
||||
out.bits.header.dst := in.bits.header.dst + UInt(ln.nMasters)
|
||||
out.bits.header.dst := in.bits.header.dst + UInt(params(LNMasters))
|
||||
out
|
||||
}
|
||||
def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
|
||||
val out = DefaultToCrossbarShim(in)
|
||||
out.bits.header.src := in.bits.header.src + UInt(ln.nMasters)
|
||||
out.bits.header.src := in.bits.header.src + UInt(params(LNMasters))
|
||||
out
|
||||
}
|
||||
|
||||
|
|
@ -112,11 +109,11 @@ class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
|
|||
typeTag[T].tpe match{
|
||||
case t if t <:< typeTag[ClientSourcedMessage].tpe => {
|
||||
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
|
||||
}
|
||||
case t if t <:< typeTag[MasterSourcedMessage].tpe => {
|
||||
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
|
||||
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
|
||||
}
|
||||
case _ => require(false, "Unknown message sourcing.")
|
||||
}
|
||||
|
|
|
|||
2
uncore
2
uncore
|
|
@ -1 +1 @@
|
|||
Subproject commit ebe0f493a62641a71caec9f2959a4f57e2c16b4e
|
||||
Subproject commit e2f3606041d97eedb10964e48e57b4b093ab73c6
|
||||
Loading…
Reference in New Issue