New uncore config objects. Backends get their own file. Simplify fpga uncore.
This commit is contained in:
Henry Cook
parent
3d4273954a
commit
224e286dd3
2
rocket
2
rocket
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@ -1 +1 @@
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Subproject commit 23a104b04472df241ca3074d0adf45c93d3da223
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Subproject commit 6a2c51c405a8687f40e229846a27c6cdb788f221
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@ -0,0 +1,69 @@
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package referencechip
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import Chisel._
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import ReferenceChipBackend._
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import scala.collection.mutable.HashMap
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object ReferenceChipBackend {
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val initMap = new HashMap[Module, Bool]()
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}
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class ReferenceChipBackend extends VerilogBackend
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{
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initMap.clear()
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override def emitPortDef(m: MemAccess, idx: Int) = {
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val res = new StringBuilder()
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for (node <- m.mem.inputs) {
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if(node.name.contains("init"))
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res.append(" .init(" + node.name + "),\n")
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}
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(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
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}
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def addMemPin(c: Module) = {
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for (mod <- Module.components; node <- mod.nodes) {
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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connectMemPin(c, node.component, node)
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}
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}
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}
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def connectMemPin(topC: Module, c: Module, p: Node): Unit = {
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var isNewPin = false
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val compInitPin =
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if (initMap.contains(c)) {
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initMap(c)
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} else {
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isNewPin = true
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val res = Bool(INPUT)
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res.isIo = true
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res
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}
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p.inputs += compInitPin
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if (isNewPin) {
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compInitPin.setName("init")
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c.io.asInstanceOf[Bundle] += compInitPin
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compInitPin.component = c
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initMap += (c -> compInitPin)
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connectMemPin(topC, c.parent, compInitPin)
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}
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}
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def addTopLevelPin(c: Module) = {
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val init = Bool(INPUT)
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init.isIo = true
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init.setName("init")
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init.component = c
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c.io.asInstanceOf[Bundle] += init
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initMap += (c -> init)
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}
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transforms += ((c: Module) => addTopLevelPin(c))
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transforms += ((c: Module) => addMemPin(c))
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transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
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}
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class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform
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@ -4,9 +4,6 @@ import Chisel._
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import uncore._
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import rocket._
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import rocket.Util._
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import ReferenceChipBackend._
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import scala.collection.mutable.HashMap
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import DRAMModel._
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object DesignSpaceConstants {
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val NTILES = 1
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@ -44,69 +41,6 @@ import DesignSpaceConstants._
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import MemoryConstants._
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import TileLinkSizeConstants._
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object ReferenceChipBackend {
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val initMap = new HashMap[Module, Bool]()
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}
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class ReferenceChipBackend extends VerilogBackend
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{
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initMap.clear()
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override def emitPortDef(m: MemAccess, idx: Int) = {
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val res = new StringBuilder()
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for (node <- m.mem.inputs) {
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if(node.name.contains("init"))
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res.append(" .init(" + node.name + "),\n")
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}
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(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
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}
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def addMemPin(c: Module) = {
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for (mod <- Module.components; node <- mod.nodes) {
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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connectMemPin(c, node.component, node)
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}
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}
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}
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def connectMemPin(topC: Module, c: Module, p: Node): Unit = {
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var isNewPin = false
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val compInitPin =
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if (initMap.contains(c)) {
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initMap(c)
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} else {
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isNewPin = true
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val res = Bool(INPUT)
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res.isIo = true
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res
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}
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p.inputs += compInitPin
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if (isNewPin) {
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compInitPin.setName("init")
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c.io.asInstanceOf[Bundle] += compInitPin
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compInitPin.component = c
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initMap += (c -> compInitPin)
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connectMemPin(topC, c.parent, compInitPin)
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}
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}
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def addTopLevelPin(c: Module) = {
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val init = Bool(INPUT)
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init.isIo = true
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init.setName("init")
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init.component = c
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c.io.asInstanceOf[Bundle] += init
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initMap += (c -> init)
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}
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transforms += ((c: Module) => addTopLevelPin(c))
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transforms += ((c: Module) => addMemPin(c))
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transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
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}
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class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform
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class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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{
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implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif)
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@ -120,13 +54,19 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
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}
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val refill_cycles = tl.dataBits/mif.dataBits
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val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
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val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
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val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
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//val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, refill_cycles))
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val mem_serdes = Module(new MemSerdes(htif_width))
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val (llc, masterEndpoints) = if(conf.useDRAMSideLLC) {
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val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
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val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
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val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
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refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
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val mes = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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(llc, mes)
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} else {
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val llc = Module(new DRAMSideLLCNull(16, refill_cycles))
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val mes = (0 until ln.nMasters).map(i => Module(new L2HellaCache(i)))
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(llc, mes)
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}
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val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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val net = Module(new ReferenceChipCrossbarNetwork)
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
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@ -145,6 +85,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
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conv.io.mem.resp <> llc.io.cpu.resp
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// mux between main and backup memory ports
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val mem_serdes = Module(new MemSerdes(htif_width))
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val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
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mem_cmdq.io.enq <> llc.io.mem.req_cmd
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mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
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@ -168,7 +109,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
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io.mem_backup <> mem_serdes.io.narrow
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}
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case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int)
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case class UncoreConfiguration(l2: L2CacheConfig, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int, useDRAMSideLLC: Boolean)
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class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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{
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@ -200,7 +141,7 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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case ((outer, client), i) =>
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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}
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@ -277,9 +218,9 @@ class Top extends Module {
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writeMaskBits = WRITE_MASK_BITS,
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wordAddrBits = SUBWORD_ADDR_BITS,
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atomicOpBits = ATOMIC_OP_BITS)
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implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
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implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as)
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS)
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implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS)
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implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = true)
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val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2))
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val dc = DCacheConfig(sets = 128, ways = 4,
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@ -306,11 +247,12 @@ class Top extends Module {
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resetSigs(i) := hl.reset
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val tile = tileList(i)
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tile.io.tilelink <> tl
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il := hl.reset
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
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tile.io.host.id := i
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
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hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
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@ -327,5 +269,3 @@ class Top extends Module {
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io.mem_backup_en <> uncore.io.mem_backup_en
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io.mem <> uncore.io.mem
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}
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@ -1,14 +1,13 @@
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package referencechip
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import Chisel._
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import Node._
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import uncore._
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import rocket._
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import DRAMModel._
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import DRAMModel.MemModelConstants._
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class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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{
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class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
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extends Module {
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implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif)
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val io = new Bundle {
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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@ -17,28 +16,23 @@ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration)
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val mem = new MemIO
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}
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val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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val master = Module(new L2CoherenceAgent(0))
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val net = Module(new ReferenceChipCrossbarNetwork)
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end }
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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net.io.masters.head <> master.io.client
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master.io.incoherent zip io.incoherent map { case (m, c) => m := c }
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val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
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if(ln.nMasters > 1) {
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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} else {
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conv.io.uncached <> masterEndpoints.head.io.master
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}
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io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
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conv.io.uncached <> master.io.master
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io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
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io.mem.req_data <> Queue(conv.io.mem.req_data, tl.dataBits/mif.dataBits)
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conv.io.mem.resp <> Queue(io.mem.resp)
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}
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class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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{
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case class FPGAUncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nSCR: Int, offsetBits: Int)
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class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
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extends Module {
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implicit val (tl, ln, mif) = (conf.tl, conf.tl.ln, conf.mif)
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val io = new Bundle {
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val host = new HostIO(htif_width)
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@ -55,16 +49,11 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
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outmemsys.io.mem <> io.mem
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// Add networking headers and endpoint queues
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def convertAddrToBank(addr: Bits): UInt = {
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require(conf.bankIdLsb + log2Up(conf.nBanks) < conf.mif.addrBits, {println("Invalid bits for bank multiplexing.")})
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addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
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}
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(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
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case ((outer, client), i) =>
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i))
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, false))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, false))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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}
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@ -81,17 +70,12 @@ import MemoryConstants._
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class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
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class FPGATop extends Module {
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val ntiles = 1
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val nmshrs = 2
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val htif_width = 16
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
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val io = new FPGATopIO(htif_width)
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val co = new MESICoherence
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val ntiles = 1
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val nbanks = 1
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val nmshrs = 2
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implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1)
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implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
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implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
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implicit val tl = TileLinkConfiguration(co = co, ln = ln,
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addrBits = as.paddrBits-OFFSET_BITS,
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@ -102,13 +86,16 @@ class FPGATop extends Module {
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wordAddrBits = SUBWORD_ADDR_BITS,
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atomicOpBits = ATOMIC_OP_BITS)
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implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
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implicit val uc = UncoreConfiguration(l2, tl, mif, ntiles, nbanks, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS)
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
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implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = OFFSET_BITS)
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val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8))
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val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2))
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val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1)
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val rc = RocketConfiguration(tl, as, ic, dc, fpu = None,
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fastMulDiv = false)
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val io = new FPGATopIO(htif_width)
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val resetSigs = Vec.fill(uc.nTiles){Bool()}
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val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
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val uncore = Module(new FPGAUncore(htif_width))
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@ -6,24 +6,25 @@ import scala.reflect._
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import scala.reflect.runtime.universe._
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object TileLinkHeaderOverwriter {
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def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
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def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = in.clone.asDirectionless
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out.bits.payload := in.bits.payload
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out.bits.header.src := UInt(clientId)
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out.bits.header.dst := in.bits.header.dst
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out.bits.header.dst := (if(passThrough) in.bits.header.dst else UInt(0))
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out.valid := in.valid
|
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in.ready := out.ready
|
||||
out
|
||||
}
|
||||
def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
|
||||
val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId)
|
||||
val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false)
|
||||
out.bits.header.dst := (if(nBanks > 1) addrConvert(in.bits.payload.addr) else UInt(0))
|
||||
out
|
||||
}
|
||||
}
|
||||
|
||||
class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO]()(conf.tl.ln) {
|
||||
implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
|
||||
class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
|
||||
extends LogicalNetwork[TileLinkIO]()(conf.ln) {
|
||||
implicit val (ln, co) = (conf.ln, conf.co)
|
||||
val io = new Bundle {
|
||||
val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip}
|
||||
val masters = Vec.fill(ln.nMasters){new TileLinkIO}
|
||||
|
|
|
|||
2
uncore
2
uncore
|
|
@ -1 +1 @@
|
|||
Subproject commit 4ca76ebaad5e796121fcb6843b00a6e5da25cd6f
|
||||
Subproject commit 181a35962b3ed19f8687551568300a0a4039eb11
|
||||
Loading…
Reference in New Issue