First cut at using new chisel parameters for toplevel parameters and fpu
This commit is contained in:
Adam Izraelevitz
parent
fcd68364ff
commit
08d81d0892
2
chisel
2
chisel
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@ -1 +1 @@
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Subproject commit 54ad639f11a6ac3459dad4d81e007b3712bd66ba
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Subproject commit e600be365d8fc5a9a868ed40ad72489817e79b44
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@ -2,6 +2,8 @@ all: emulator
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base_dir = ..
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sim_dir = .
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PROJECT = referencechip
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CONFIG = DefaultCPPConfig
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include $(base_dir)/Makefrag
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@ -15,14 +17,14 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfes
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OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
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DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
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CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src
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CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src --configInstance $(PROJECT).$(CONFIG)
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CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
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generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
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cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
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cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS)"
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generated-src-debug/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
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cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
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cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS_DEBUG)"
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$(MODEL).o: %.o: generated-src/%.h
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$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp))
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2
rocket
2
rocket
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@ -1 +1 @@
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Subproject commit fd9bea861cf8cb83ff57c419f8a20964742baba5
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Subproject commit 1b01778c1743d779966829e0edfb904528ac472f
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@ -5,42 +5,48 @@ import uncore._
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import rocket._
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import rocket.Util._
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object DesignSpaceConstants {
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val NTILES = 1
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val NBANKS = 1
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val HTIF_WIDTH = 16
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val ENABLE_SHARING = true
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val ENABLE_CLEAN_EXCLUSIVE = true
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val USE_DRAMSIDE_LLC = true
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val HAS_FPU = true
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val NL2_REL_XACTS = 1
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val NL2_ACQ_XACTS = 7
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val NMSHRS = 2
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class DefaultVLSIConfig extends DefaultConfig
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class DefaultFPGAConfig extends DefaultConfig
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class DefaultCPPConfig extends DefaultConfig
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class DefaultConfig extends ChiselConfig {
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val top:World.TopDefs = {
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(pname,site,here) => pname match {
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//DesignSpaceConstants
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case "NTILES" => 1
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case "NBANKS" => 1
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case "HTIF_WIDTH" => 16
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case "ENABLE_SHARING" => true
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case "ENABLE_CLEAN_EXCLUSIVE" => true
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case "USE_DRAMSIDE_LLC" => true
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case "NL2_REL_XACTS" => 1
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case "NL2_ACQ_XACTS" => 7
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case "NMSHRS" => 2
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//FPUConstants
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case HasFPU => true
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case FPUParams => Alter({
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case SFMALatency => 2
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case DFMALatency => 3
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})
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//MemoryConstants
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case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 //TODO: How configurable is this really?
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case "OFFSET_BITS" => log2Up(here[Int]("CACHE_DATA_SIZE_IN_BYTES"))
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case "PADDR_BITS" => 32
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case "VADDR_BITS" => 43
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case "PGIDX_BITS" => 13
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case "ASID_BITS" => 7
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case "PERM_BITS" => 6
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case "MEM_TAG_BITS" => 5
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case "MEM_DATA_BITS" => 128
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case "MEM_ADDR_BITS" => here[Int]("PADDR_BITS") - here[Int]("OFFSET_BITS")
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case "MEM_DATA_BEATS" => 4
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//TileLinkSizeConstants
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case "WRITE_MASK_BITS" => 6
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case "SUBWORD_ADDR_BITS" => 3
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case "ATOMIC_OP_BITS" => 4
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}
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}
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}
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object MemoryConstants {
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val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 //TODO: How configurable is this really?
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val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES)
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val PADDR_BITS = 32
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val VADDR_BITS = 43
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val PGIDX_BITS = 13
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val ASID_BITS = 7
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val PERM_BITS = 6
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val MEM_TAG_BITS = 5
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val MEM_DATA_BITS = 128
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val MEM_ADDR_BITS = PADDR_BITS - OFFSET_BITS
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val MEM_DATA_BEATS = 4
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}
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object TileLinkSizeConstants {
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val WRITE_MASK_BITS = 6
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val SUBWORD_ADDR_BITS = 3
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val ATOMIC_OP_BITS = 4
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}
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import DesignSpaceConstants._
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import MemoryConstants._
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import TileLinkSizeConstants._
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class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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{
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@ -192,55 +198,54 @@ class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends To
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class MemDessert extends Module {
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS)
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val io = new MemDesserIO(HTIF_WIDTH)
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val x = Module(new MemDesser(HTIF_WIDTH))
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implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS"))
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val io = new MemDesserIO(params[Int]("HTIF_WIDTH"))
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val x = Module(new MemDesser(params[Int]("HTIF_WIDTH")))
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io.narrow <> x.io.narrow
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io.wide <> x.io.wide
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}
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class Top extends Module {
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val dir = new FullRepresentation(NTILES+1)
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val co = if(ENABLE_SHARING) {
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if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence(dir)
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val dir = new FullRepresentation(params[Int]("NTILES")+1)
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val co = if(params[Boolean]("ENABLE_SHARING")) {
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if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir)
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else new MSICoherence(dir)
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} else {
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if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence(dir)
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if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir)
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else new MICoherence(dir)
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}
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implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)
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implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
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implicit val ln = LogicalNetworkConfiguration(log2Up(params[Int]("NTILES"))+1, params[Int]("NBANKS"), params[Int]("NTILES")+1)
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implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS"))
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implicit val tl = TileLinkConfiguration(co = co, ln = ln,
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addrBits = as.paddrBits-OFFSET_BITS,
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clientXactIdBits = log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS),
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masterXactIdBits = 2*log2Up(NMSHRS*NTILES+1),
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dataBits = CACHE_DATA_SIZE_IN_BYTES*8,
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writeMaskBits = WRITE_MASK_BITS,
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wordAddrBits = SUBWORD_ADDR_BITS,
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atomicOpBits = ATOMIC_OP_BITS)
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implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as)
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS)
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implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = USE_DRAMSIDE_LLC)
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addrBits = as.paddrBits-params[Int]("OFFSET_BITS"),
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clientXactIdBits = log2Up(params[Int]("NL2_REL_XACTS")+params[Int]("NL2_ACQ_XACTS")),
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masterXactIdBits = 2*log2Up(params[Int]("NMSHRS")*params[Int]("NTILES")+1),
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dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8,
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writeMaskBits = params[Int]("WRITE_MASK_BITS"),
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wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"),
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atomicOpBits = params[Int]("ATOMIC_OP_BITS"))
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implicit val l2 = L2CacheConfig(512, 8, 1, 1, params[Int]("NL2_REL_XACTS"), params[Int]("NL2_ACQ_XACTS"), tl, as)
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implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS"))
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implicit val uc = UncoreConfiguration(l2, tl, mif, params[Int]("NTILES"), params[Int]("NBANKS"), bankIdLsb = 5, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"), useDRAMSideLLC = params[Boolean]("USE_DRAMSIDE_LLC"))
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val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2))
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val dc = DCacheConfig(sets = 128, ways = 4,
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tl = tl, as = as,
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ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17,
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ntlb = 8, nmshr = params[Int]("NMSHRS"), nrpq = 16, nsdq = 17,
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reqtagbits = -1, databits = -1)
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val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
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val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
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val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
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val rc = RocketConfiguration(tl, as, ic, dc, fpu
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val rc = RocketConfiguration(tl, as, ic, dc
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// rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
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)
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val io = new VLSITopIO(HTIF_WIDTH)
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val io = new VLSITopIO(params[Int]("HTIF_WIDTH"))
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val resetSigs = Vec.fill(uc.nTiles){Bool()}
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val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
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val uncore = Module(new Uncore(HTIF_WIDTH))
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val uncore = Module(new Uncore(params[Int]("HTIF_WIDTH")))
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for (i <- 0 until uc.nTiles) {
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val hl = uncore.io.htif(i)
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@ -62,11 +62,6 @@ class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
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htif.io.host.in <> io.host.in
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}
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import MemoryConstants._
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import TileLinkSizeConstants._
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import MemoryConstants._
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class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
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class FPGATop extends Module {
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@ -76,22 +71,22 @@ class FPGATop extends Module {
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val co = new MESICoherence(new FullRepresentation(ntiles+1))
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implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
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implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
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implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS"))
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implicit val tl = TileLinkConfiguration(co = co, ln = ln,
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addrBits = as.paddrBits-OFFSET_BITS,
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addrBits = as.paddrBits-params[Int]("OFFSET_BITS"),
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clientXactIdBits = log2Up(1+8),
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masterXactIdBits = 2*log2Up(2*1+1),
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dataBits = CACHE_DATA_SIZE_IN_BYTES*8,
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writeMaskBits = WRITE_MASK_BITS,
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wordAddrBits = SUBWORD_ADDR_BITS,
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atomicOpBits = ATOMIC_OP_BITS)
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dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8,
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writeMaskBits = params[Int]("WRITE_MASK_BITS"),
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wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"),
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atomicOpBits = params[Int]("ATOMIC_OP_BITS"))
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implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
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implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = OFFSET_BITS)
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implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS"))
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implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"))
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val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2))
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val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1)
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val rc = RocketConfiguration(tl, as, ic, dc, fpu = None,
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val rc = RocketConfiguration(tl, as, ic, dc,
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fastMulDiv = false)
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val io = new FPGATopIO(htif_width)
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@ -173,7 +168,7 @@ class Slave extends AXISlave
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// write cr1 -> mem.resp (nonblocking)
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val in_count = Reg(init=UInt(0, log2Up(memw/dw)))
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val rf_count = Reg(init=UInt(0, log2Up(CACHE_DATA_SIZE_IN_BYTES*8/memw)))
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val rf_count = Reg(init=UInt(0, log2Up(params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8/memw)))
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require(memw % dw == 0 && isPow2(memw/dw))
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val in_reg = Reg(top.io.mem.resp.bits.data)
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top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw))
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