riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

TileLinkIO.GrantAck -> TileLinkIO.Finish

This commit is contained in:
Henry Cook 2014-04-26 15:19:25 -07:00
parent fbf6e44376
commit 3d4273954a
5 changed files with 19 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket

@ -1 +1 @@
Subproject commit 1a921d1760d7861ae60a67b659ec022a79740559
Subproject commit 23a104b04472df241ca3074d0adf45c93d3da223

2
src/main/scala/RocketChip.scala
View File

@ -200,7 +200,7 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
case ((outer, client), i) =>
outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i))
outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i))
client.grant <> Queue(outer.grant, 1, pipe = true)
client.probe <> Queue(outer.probe)
}

114
src/main/scala/fpga.scala
View File

@ -64,7 +64,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
case ((outer, client), i) =>
outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i))
outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i))
client.grant <> Queue(outer.grant, 1, pipe = true)
client.probe <> Queue(outer.probe)
}
@ -76,18 +76,17 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
import MemoryConstants._
import TileLinkSizeConstants._
class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extends Module {
val io = new Bundle {
val host_in = new DecoupledIO(new HostPacket(htif_width)).flip()
val host_out = new DecoupledIO(new HostPacket(htif_width))
val host_clk = Bool(OUTPUT)
val host_clk_edge = Bool(OUTPUT)
val host_debug_stats_pcr = Bool(OUTPUT)
val mem_req_cmd = new DecoupledIO(new MemReqCmd())
val mem_req_data = new DecoupledIO(new MemData())
val mem_resp = (new DecoupledIO(new MemResp())).flip()
}
import MemoryConstants._
class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
class FPGATop extends Module {
val htif_width = 16
implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
val io = new FPGATopIO(htif_width)
val co = new MESICoherence
val ntiles = 1
val nbanks = 1
@ -131,94 +130,9 @@ class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extend
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
}
io.host_in.ready := uncore.io.host.in.ready
uncore.io.host.in.bits := io.host_in.bits.data
uncore.io.host.in.valid := io.host_in.valid
uncore.io.host.out.ready := io.host_out.ready
io.host_out.bits.data := uncore.io.host.out.bits
io.host_out.valid := uncore.io.host.out.valid
io.host_clk := uncore.io.host.clk
io.host_clk_edge := uncore.io.host.clk_edge
io.host_debug_stats_pcr := uncore.io.host.debug_stats_pcr
io.mem_req_cmd <> uncore.io.mem.req_cmd
io.mem_req_data <> uncore.io.mem.req_data
io.mem_resp <> uncore.io.mem.resp
}
import MemoryConstants._
class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
class FPGATop extends Module {
val htif_width = 16
implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
val deviceWidth = ROW_WIDTH/mif.dataBits
implicit val mc = MemoryControllerConfiguration(deviceWidth, (if(deviceWidth == 4) 0 else log2Up(deviceWidth/4)), mif)
val io = new FPGATopIO(htif_width)
val referenceChip = Module(new Fame1Wrapper(new ReferenceChip(htif_width)))
val dramModel = Module(new DRAMSystemWrapper())
//dram model parameters setup
dramModel.io.params.tRAS := UInt(4)
dramModel.io.params.tRCD := UInt(4)
dramModel.io.params.tRP := UInt(4)
dramModel.io.params.tCCD := UInt(4)
dramModel.io.params.tRTP := UInt(4)
dramModel.io.params.tWTR := UInt(4)
dramModel.io.params.tWR := UInt(4)
dramModel.io.params.tRRD := UInt(4)
//host to reference chip connections
referenceChip.DecoupledIOs("host_in").host_valid := Bool(true)
referenceChip.DecoupledIOs("host_in").target.bits := io.host.in.bits
referenceChip.DecoupledIOs("host_in").target.valid := io.host.in.valid
io.host.in.ready := referenceChip.DecoupledIOs("host_in").host_ready && referenceChip.DecoupledIOs("host_in").target.ready
io.host.out.valid := referenceChip.DecoupledIOs("host_out").host_valid && referenceChip.DecoupledIOs("host_out").target.valid
io.host.out.bits := referenceChip.DecoupledIOs("host_out").target.bits
referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready
referenceChip.DecoupledIOs("host_out").host_ready := Bool(true)
io.host.clk := referenceChip.DebugIOs("host_clk").toBits()(0)
io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge").toBits()(0)
io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr").toBits()(0)
//reference chip to dram model connections
val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd()))
val mem_req_data_queue = Module(new FameQueue(8)(new MemData()))
val mem_resp_queue = Module(new FameQueue(8)(new MemResp()))
//cmd queue
FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_cmd"), mem_req_cmd_queue.io.enq, new MemReqCmd)
mem_req_cmd_queue.io.deq <> dramModel.io.memReqCmd
//data queue
FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_data"), mem_req_data_queue.io.enq, new MemData)
mem_req_data_queue.io.deq <> dramModel.io.memReqData
//resp queue
mem_resp_queue.io.enq <> dramModel.io.memResp
FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_resp"), mem_resp_queue.io.deq, new MemResp)
//dram model to outside memory connections
val host_mem_cmd_queue = Module(new Queue(new MemReqCmd, 2))
val host_mem_data_queue = Module(new Queue(new MemData, mif.dataBeats))
val host_mem_resp_queue = Module(new Queue(new MemResp, mif.dataBeats))
host_mem_cmd_queue.io.enq <> dramModel.io.mem.req_cmd
host_mem_cmd_queue.io.deq <> io.mem.req_cmd
host_mem_data_queue.io.enq <> dramModel.io.mem.req_data
host_mem_data_queue.io.deq <> io.mem.req_data
host_mem_resp_queue.io.enq <> io.mem.resp
host_mem_resp_queue.io.deq <> dramModel.io.mem.resp
uncore.io.host <> io.host
uncore.io.mem <> io.mem
}
abstract class AXISlave extends Module {

4
src/main/scala/network.scala
View File

@ -36,7 +36,7 @@ class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends L
val relNet = Module(new BasicCrossbar(new Release))
val prbNet = Module(new BasicCrossbar(new Probe))
val gntNet = Module(new BasicCrossbar(new Grant))
val ackNet = Module(new BasicCrossbar(new GrantAck))
val ackNet = Module(new BasicCrossbar(new Finish))
// Aliases for the various network IO bundle types
type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
@ -125,5 +125,5 @@ class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends L
doFIFOHookups(relNet.io, (tl: TileLinkIO) => tl.release)
doFIFOHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
doFIFOHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack)
doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.finish)
}

2
uncore

@ -1 +1 @@
Subproject commit f6a4cb6ecfc1854d5100aed72bcb7978ea025c13
Subproject commit 4ca76ebaad5e796121fcb6843b00a6e5da25cd6f