riscv/rocket-chip
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add verilog target to build without simulator

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This commit is contained in:
Scott Beamer 2014-09-03 17:28:45 -07:00
parent 13b6ec4712
commit 6c6f5a3843
3 changed files with 8 additions and 4 deletions
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4
Makefrag
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@ -40,6 +40,10 @@ $(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen
$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert"
# Generic Verilog
.PHONY: verilog
verilog: $(sim_vsrcs)
#--------------------------------------------------------------------
# DRAMSim2
#--------------------------------------------------------------------

4
fsim/Makefile
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@ -15,11 +15,11 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim
all: $(simv)
clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*

4
vsim/Makefile
View File

@ -15,11 +15,11 @@ vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim
all: $(simv)
clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*