riscv/rocket-chip
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  • 0f51ca4c10 Merge pull request #35 from ucb-bar/dma Howard Mao 2015-12-22 10:33:59 -0500
  • b8d0376d3f Merge pull request #1 from ucb-bar/dma Howard Mao 2015-12-22 10:33:48 -0500
  • dbe68056d9 Merge pull request #21 from ucb-bar/dma Howard Mao 2015-12-22 10:33:28 -0500
  • 09f3c5a6e3 Merge pull request #6 from ucb-bar/dma Henry Cook 2015-12-21 13:54:38 -0800
  • 8190bf6e18 implement DMA unit Howard Mao 2015-11-17 18:21:52 -0800
  • 872b162e1b implement DMA engine Howard Mao 2015-11-17 18:13:50 -0800
  • 24eecee148 add DMA test Howard Mao 2015-11-18 20:53:36 -0800
  • 304d8b814a Implement client-side DMA controller Howard Mao 2015-11-17 18:14:30 -0800
  • 8a61177224 generalize TwoWayCounter Howard Mao 2015-11-19 15:04:09 -0800
  • 1a272677ca more fixes to L2 cache Howard Mao 2015-12-16 21:06:39 -0800
  • 4858ca9a60 add a regression to test proper writeback Howard Mao 2015-12-16 21:05:56 -0800
  • a48237f36d get rid of the rest of the PutBlock special casing in L2 Howard Mao 2015-12-16 20:56:29 -0800
  • 01a3447989 Remove duplicate PseudoLRU class from rocket TLB Albert Magyar 2015-12-16 16:12:47 -0800
  • 560fdc19a8 add PLRU replacement option to L2 cache Howard Mao 2015-12-16 10:24:57 -0800
  • 922b1adc9c Add optional PLRU replacement to the L2 Albert Magyar 2015-12-10 16:40:16 -0800
  • 7ad9deeaee Fix issues with request merging in L2 cache and add regression tests Howard Mao 2015-12-14 20:01:22 -0800
  • 176d3c890c add some more regression tests Howard Mao 2015-12-14 19:45:20 -0800
  • ddc79674f9 fix some issues with cache request merging Howard Mao 2015-12-15 18:17:19 -0800
  • c080e82e92 Merge pull request #34 from seldridge/rocketchip-addons-build Colin Schmidt 2015-12-09 11:57:19 -0800
  • e50e4d4c84 build.scala uses space-delimited ROCKETCHIP_ADDONS Schuyler Eldridge 2015-12-09 14:17:16 -0500
  • 91be080526 Merge pull request #32 from ucb-bar/javamaxpermsize Andrew Waterman 2015-12-07 13:58:41 -0800
  • c5e9558571 Double Java MaxPermSize. Jim Lawson 2015-12-07 12:05:06 -0800
  • 0c91e00676 move GroundTest configs to a separate file Howard Mao 2015-12-06 03:01:05 -0800
  • e71293e2ae fix bug in narrower logic Howard Mao 2015-12-06 02:58:12 -0800
  • 484e8ce20b add regression tests for catching specific memory bugs Howard Mao 2015-12-06 02:57:45 -0800
  • 4f5dabcda2 add SCR file to device tree Howard Mao 2015-12-04 12:16:25 -0800
  • c57639b23f reverse order of RWX bits for compatibility Howard Mao 2015-12-05 00:26:16 -0800
  • 6fc1e92708 add option to print cycle count regardless of exit status Howard Mao 2015-12-04 12:04:13 -0800
  • 93aa370b87 yunsup's fix for dgemm-opt assertion failure Sagar Karandikar 2015-12-03 14:03:10 -0800
  • f35b83d3ca allow configuration of rocket ICache buffering Howard Mao 2015-12-02 17:18:39 -0800
  • 7690de07e1 allow icache to configure which side of the way mux gets buffered Howard Mao 2015-12-02 17:17:49 -0800
  • 369ee74a2c change names of RoCC tilelink interfaces to be more sensible Howard Mao 2015-12-02 16:28:23 -0800
  • ebf2417a32 rocc-fpu-port merged into master for rocket Howard Mao 2015-12-02 09:02:43 -0800
  • f67b02fadb Merge branch 'rocc-fpu-port' Howard Mao 2015-12-02 08:52:15 -0800
  • 73b0263663 disconnect fpu port if no fpu-using RoCC accelerators Howard Mao 2015-12-01 20:41:58 -0800
  • 3f8f726296 make rocc build independent from parameter structure Howard Mao 2015-12-01 18:47:52 -0800
  • dcca0b1d86 fix up FPU connection Howard Mao 2015-12-01 18:14:58 -0800
  • 08f77ca90d Merge branch 'master' into rocc-fpu-port Howard Mao 2015-12-01 18:00:28 -0800
  • cdc476a370 change Rocc parameterization Howard Mao 2015-12-01 17:55:07 -0800
  • e76dfa55f7 change the way rocc is parameterized Howard Mao 2015-12-01 17:54:56 -0800
  • e0d849fec5 Fix zscale testing Andrew Waterman 2015-12-01 17:31:10 -0800
  • 4833d41dbc make the connection of FPU ports optional per accelerator Howard Mao 2015-12-01 16:48:05 -0800
  • 5eeb8969f6 fix zscale build (run still fails) Andrew Waterman 2015-12-01 16:20:17 -0800
  • c8c68e75bb base NGenerators on NTiles, not the other way around Howard Mao 2015-12-01 15:26:09 -0800
  • 0b15b19381 add arbiter for FPU Howard Mao 2015-12-01 10:22:31 -0800
  • 1db2da00f3 Merge branch 'master' into rocc-fpu-port Howard Mao 2015-11-30 19:18:58 -0800
  • e4043570bd bump groundtest and hardfloat Howard Mao 2015-11-30 18:06:15 -0800
  • 40d68406d6 use xlen parameter for ALU Howard Mao 2015-11-30 18:04:44 -0800
  • e80340198a use implicit parameters for ALU Howard Mao 2015-11-30 17:35:33 -0800
  • ec4ade988b [travis] add multiple configs including rocc Colin Schmidt 2015-11-28 07:17:49 -0800
  • 7259239ba4 Merge pull request #31 from ucb-bar/multirocc Colin Schmidt 2015-11-28 08:56:07 -0500
  • 90991014a0 Merge pull request #19 from ucb-bar/multirocc Colin Schmidt 2015-11-28 08:56:04 -0500
  • 7083576156 fix typo in NastiErrorSlave Howard Mao 2015-11-26 12:57:04 -0800
  • 23f0756978 implement support for multiple RoCC accelerators Howard Mao 2015-11-25 16:02:54 -0800
  • 9256239206 implement support for multiple RoCC accelerators Howard Mao 2015-11-25 16:02:27 -0800
  • 58b0a86834 some modifications to AccumulatorExample Howard Mao 2015-11-25 14:04:28 -0800
  • e25a020e60 Construct device tree ROM in MMIO region Andrew Waterman 2015-11-25 21:10:09 -0800
  • e52685f2e9 Fix LoadGen zero flag Andrew Waterman 2015-11-25 20:52:30 -0800
  • 27df04354f Add ROM with NASTI interface Andrew Waterman 2015-11-25 20:04:31 -0800
  • 49d93da87e Factor out more common zscale code Andrew Waterman 2015-11-24 19:17:21 -0800
  • e203b8b378 Make ALU generic for zscale Andrew Waterman 2015-11-24 19:17:07 -0800
  • 52b25c3da0 Factor out more common zscale code Andrew Waterman 2015-11-24 18:34:03 -0800
  • 5294e94794 Remove CSR back pressure ability Andrew Waterman 2015-11-24 18:28:14 -0800
  • 4616db4695 Make RegFile/ImmGen usable by zscale Andrew Waterman 2015-11-24 18:27:07 -0800
  • 1761db3272 Factor out some common code from zscale Andrew Waterman 2015-11-24 18:14:06 -0800
  • 6d1bf5c014 Use generic LoadGen/StoreGen Andrew Waterman 2015-11-24 18:13:33 -0800
  • 57e82442a1 Make LoadGen and StoreGen generic Andrew Waterman 2015-11-24 18:12:11 -0800
  • ec6bfde9a3 fix WritebackUnit issue in uncore Howard Mao 2015-11-21 16:11:22 -0800
  • ee6514e4f4 make sure WritebackUnit sends correct probe addresses Howard Mao 2015-11-21 15:55:11 -0800
  • 04383a31f5 Revert "make sure L2MetadataArray assigns unoccupied way if available" Howard Mao 2015-11-21 10:35:40 -0800
  • 158d1d870c do all the writes before doing the gets in GeneratorTest Howard Mao 2015-11-21 09:42:00 -0800
  • 65632c875a Merge branch 'master' into rocc-fpu-port Sagar Karandikar 2015-11-21 02:24:38 -0800
  • 9d50f37289 fix unused set issue for multiple L2 cache banks Howard Mao 2015-11-20 23:26:28 -0800
  • 3c95afebc6 Shift set index for multi-bank configurations Howard Mao 2015-11-20 23:21:14 -0800
  • 55a85cc67a make sure wmask is passed for PutBlock in broadcast hub Howard Mao 2015-11-20 14:09:24 -0800
  • 941b64cd62 make partial write-masking PutBlock constructor always set alloc bit Howard Mao 2015-11-20 13:34:07 -0800
  • b0a06a77db fix a few Chisel3 compat issues Howard Mao 2015-11-20 13:33:15 -0800
  • ad3b7fd0e1 adjust CacheFillTest configuration Howard Mao 2015-11-19 10:52:14 -0800
  • 24f7b9f472 make sure L2MetadataArray assigns unoccupied way if available Howard Mao 2015-11-19 10:45:54 -0800
  • 4806f72b08 add CacheFillTest to check L2 conflict misses Howard Mao 2015-11-19 00:16:28 -0800
  • 49c6b1ad1c add CacheFillTest Howard Mao 2015-11-19 00:15:36 -0800
  • 640544ea5a generalize test harness Howard Mao 2015-11-18 22:54:05 -0800
  • f325874420 make sure timeout doesn't trigger spuriously on reset Howard Mao 2015-11-18 22:53:50 -0800
  • 3514b6eb87 add some more useful configurations Howard Mao 2015-11-18 17:07:01 -0800
  • 379d43d5f4 make MultiChannel routing more performant Howard Mao 2015-11-18 17:06:38 -0800
  • ea8ba49805 improve memory system: specialize MultiChannel routing Yunsup Lee 2015-11-18 21:58:22 -0800
  • 8bc90ab9bd separate out common functionality Howard Mao 2015-11-18 20:53:19 -0800
  • e50c7ad306 add NASTI error assertions back in Howard Mao 2015-11-18 17:05:54 -0800
  • e7e281275a implement MultiChannel routing in a specialized (and more performant) way Howard Mao 2015-11-18 12:15:56 -0800
  • 94d2dd3053 Merge remote-tracking branch 'origin/master' into rocc-fpu-port Yunsup Lee 2015-11-16 23:29:25 -0800
  • 2b977325e3 Make prefetch type available in a_type, issue probeInvalidates for putPrefetches Henry Cook 2015-11-16 23:26:13 -0800
  • 5195a5b891 Remove IPI network Andrew Waterman 2015-11-16 21:53:14 -0800
  • d426ecee78 Remove IPI network Andrew Waterman 2015-11-16 21:52:24 -0800
  • 0f092b9b59 Remove IPI network Andrew Waterman 2015-11-16 21:51:43 -0800
  • 0290635454 amo_shift_bits -> amo_shift_bytes Henry Cook 2015-11-16 19:07:58 -0800
  • 485f1b7bd7 bump uncore Henry Cook 2015-11-16 18:14:03 -0800
  • 64aaf71b06 L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type. Henry Cook 2015-11-16 13:23:17 -0800
  • 03fa06e6e7 fix prefetch lockup on L2 hit Henry Cook 2015-11-15 12:51:34 -0800
  • 5e2698adbc Merge remote-tracking branch 'origin/master' into rocc-fpu-port Yunsup Lee 2015-11-14 16:44:55 -0800
  • 8916c7e99c push rocket Yunsup Lee 2015-11-14 16:43:28 -0800