Merge branch 'master' into rocc-fpu-port
This commit is contained in:
Howard Mao
commit
1db2da00f3
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@ -78,7 +78,6 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val wdata = Bits(INPUT, xLen)
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}
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val csr_replay = Bool(OUTPUT)
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val csr_stall = Bool(OUTPUT)
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val csr_xcpt = Bool(OUTPUT)
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val eret = Bool(OUTPUT)
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@ -347,14 +346,13 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_sepc := reg_mepc
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}
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assert(PopCount(insn_ret :: insn_redirect_trap :: io.exception :: csr_xcpt :: io.csr_replay :: Nil) <= 1, "these conditions must be mutually exclusive")
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assert(PopCount(insn_ret :: insn_redirect_trap :: io.exception :: csr_xcpt :: Nil) <= 1, "these conditions must be mutually exclusive")
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when (read_time >= reg_mtimecmp) {
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reg_mip.mtip := true
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}
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io.time := reg_cycle
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io.csr_replay := false
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io.csr_stall := reg_wfi
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when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) }
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@ -43,17 +43,15 @@ object ALU
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}
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import ALU._
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class ALUIO(implicit p: Parameters) extends CoreBundle()(p) {
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val dw = Bits(INPUT, SZ_DW)
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val fn = Bits(INPUT, SZ_ALU_FN)
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val in2 = UInt(INPUT, xLen)
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val in1 = UInt(INPUT, xLen)
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val out = UInt(OUTPUT, xLen)
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val adder_out = UInt(OUTPUT, xLen)
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}
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class ALU(implicit p: Parameters) extends Module {
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val io = new ALUIO
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class ALU(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val dw = Bits(INPUT, SZ_DW)
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val fn = Bits(INPUT, SZ_ALU_FN)
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val in2 = UInt(INPUT, xLen)
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val in1 = UInt(INPUT, xLen)
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val out = UInt(OUTPUT, xLen)
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val adder_out = UInt(OUTPUT, xLen)
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}
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// ADD, SUB
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val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2)
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@ -61,19 +59,26 @@ class ALU(implicit p: Parameters) extends Module {
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// SLT, SLTU
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val cmp = cmpInverted(io.fn) ^
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Mux(cmpEq(io.fn), sum === UInt(0),
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Mux(io.in1(63) === io.in2(63), sum(63),
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Mux(cmpUnsigned(io.fn), io.in2(63), io.in1(63))))
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Mux(io.in1(xLen-1) === io.in2(xLen-1), sum(xLen-1),
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Mux(cmpUnsigned(io.fn), io.in2(xLen-1), io.in1(xLen-1))))
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// SLL, SRL, SRA
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val shamt = Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0)).toUInt
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val shin_hi_32 = Mux(isSub(io.fn), Fill(32, io.in1(31)), UInt(0,32))
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val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
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val shin_r = Cat(shin_hi, io.in1(31,0))
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val full_shamt = io.in2(log2Up(xLen)-1,0)
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val (shamt, shin_r) =
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if (xLen == 32) (full_shamt, io.in1)
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else {
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require(xLen == 64)
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val shin_hi_32 = Fill(32, isSub(io.fn) && io.in1(31))
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val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
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val shamt = Cat(full_shamt(5) & (io.dw === DW_64), full_shamt(4,0))
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(shamt, Cat(shin_hi, io.in1(31,0)))
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}
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val shin = Mux(io.fn === FN_SR || io.fn === FN_SRA, shin_r, Reverse(shin_r))
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val shout_r = (Cat(isSub(io.fn) & shin(63), shin).toSInt >> shamt)(63,0)
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val shout_r = (Cat(isSub(io.fn) & shin(xLen-1), shin).toSInt >> shamt)(xLen-1,0)
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val shout_l = Reverse(shout_r)
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val out64 =
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val out =
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Mux(io.fn === FN_ADD || io.fn === FN_SUB, sum,
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Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r,
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Mux(io.fn === FN_SL, shout_l,
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@ -82,7 +87,10 @@ class ALU(implicit p: Parameters) extends Module {
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Mux(io.fn === FN_XOR, io.in1 ^ io.in2,
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/* all comparisons */ cmp))))))
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val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
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io.out := Cat(out_hi, out64(31,0)).toUInt
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io.adder_out := sum
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io.out := out
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if (xLen > 32) {
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require(xLen == 64)
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when (io.dw === DW_32) { io.out := Cat(Fill(32, out(31)), out(31,0)) }
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}
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}
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@ -162,8 +162,8 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val req_cmd_sc = req.cmd === M_XSC
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val grant_word = Reg(UInt(width = wordBits))
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val storegen = new StoreGen64(req.typ, req.addr, req.data)
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val loadgen = new LoadGen64(req.typ, req.addr, grant_word, req_cmd_sc)
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val storegen = new StoreGen(req.typ, req.addr, req.data, 8)
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val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, 8)
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val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
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val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
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@ -200,7 +200,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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io.resp.valid := (state === s_resp)
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io.resp.bits := req
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io.resp.bits.has_data := isRead(req.cmd)
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io.resp.bits.data := loadgen.byte | req_cmd_sc
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io.resp.bits.data := loadgen.data | req_cmd_sc
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io.resp.bits.store_data := req.data
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io.resp.bits.nack := Bool(false)
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io.resp.bits.replay := io.resp.valid
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@ -815,11 +815,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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s2_req.cmd := s1_req.cmd
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}
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val misaligned =
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(((s1_req.typ === MT_H) || (s1_req.typ === MT_HU)) && (s1_req.addr(0) != Bits(0))) ||
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(((s1_req.typ === MT_W) || (s1_req.typ === MT_WU)) && (s1_req.addr(1,0) != Bits(0))) ||
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((s1_req.typ === MT_D) && (s1_req.addr(2,0) != Bits(0)))
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val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), 8).misaligned
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io.cpu.xcpt.ma.ld := s1_read && misaligned
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io.cpu.xcpt.ma.st := s1_write && misaligned
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io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
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@ -1018,7 +1014,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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// load data subword mux/sign extension
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val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits)))
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val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
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val loadgen = new LoadGen64(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
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val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, 8)
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amoalu.io.addr := s2_req.addr
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amoalu.io.cmd := s2_req.cmd
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@ -1052,7 +1048,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
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cache_resp.bits := s2_req
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cache_resp.bits.has_data := isRead(s2_req.cmd)
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cache_resp.bits.data := loadgen.byte | s2_sc_fail
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cache_resp.bits.data := loadgen.data | s2_sc_fail
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cache_resp.bits.store_data := s2_req.data
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cache_resp.bits.nack := s2_valid && s2_nack
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cache_resp.bits.replay := s2_replay
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@ -1065,7 +1061,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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mshrs.io.resp.ready := !cache_pass
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io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)
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io.cpu.resp.bits.data_word_bypass := loadgen.word
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io.cpu.resp.bits.data_word_bypass := loadgen.wordData
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io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
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io.cpu.replay_next.valid := s1_replay && s1_read
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io.cpu.replay_next.bits := s1_req.tag
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@ -58,12 +58,12 @@ abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
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}
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class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
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val regfile = Mem(UInt(width = xLen), n)
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val busy = Reg(init=Vec(Bool(false), n))
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val regfile = Mem(n, UInt(width = xLen))
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val busy = Reg(init = Vec.fill(n){Bool(false)})
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val cmd = Queue(io.cmd)
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val funct = cmd.bits.inst.funct
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val addr = cmd.bits.inst.rs2(log2Up(n)-1,0)
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val addr = cmd.bits.rs2(log2Up(n)-1,0)
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val doWrite = funct === UInt(0)
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val doRead = funct === UInt(1)
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val doLoad = funct === UInt(2)
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@ -130,3 +130,173 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
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io.dptw.req.valid := false
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io.pptw.req.valid := false
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}
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class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
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val req_addr = Reg(UInt(width = coreMaxAddrBits))
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val req_rd = Reg(io.resp.bits.rd)
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val req_offset = req_addr(pgIdxBits - 1, 0)
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val req_vpn = req_addr(coreMaxAddrBits - 1, pgIdxBits)
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val ppn = Reg(UInt(width = ppnBits))
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val error = Reg(Bool())
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val s_idle :: s_ptw_req :: s_ptw_resp :: s_resp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.cmd.ready := (state === s_idle)
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when (io.cmd.fire()) {
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req_rd := io.cmd.bits.inst.rd
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req_addr := io.cmd.bits.rs1
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state := s_ptw_req
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}
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when (io.dptw.req.fire()) { state := s_ptw_resp }
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when (state === s_ptw_resp && io.dptw.resp.valid) {
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error := io.dptw.resp.bits.error
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ppn := io.dptw.resp.bits.pte.ppn
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state := s_resp
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}
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when (io.resp.fire()) { state := s_idle }
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io.dptw.req.valid := (state === s_ptw_req)
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io.dptw.req.bits.addr := req_vpn
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io.dptw.req.bits.store := Bool(false)
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io.dptw.req.bits.fetch := Bool(false)
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io.resp.valid := (state === s_resp)
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io.resp.bits.rd := req_rd
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io.resp.bits.data := Mux(error, SInt(-1).toUInt, Cat(ppn, req_offset))
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io.busy := (state =/= s_idle)
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io.interrupt := Bool(false)
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io.mem.req.valid := Bool(false)
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io.dmem.head.acquire.valid := Bool(false)
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io.dmem.head.grant.ready := Bool(false)
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io.imem.acquire.valid := Bool(false)
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io.imem.grant.ready := Bool(false)
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io.iptw.req.valid := Bool(false)
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io.pptw.req.valid := Bool(false)
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}
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class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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with HasTileLinkParameters {
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private val blockOffset = tlBeatAddrBits + tlByteAddrBits
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val needle = Reg(UInt(width = 8))
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val addr = Reg(UInt(width = coreMaxAddrBits))
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val count = Reg(UInt(width = xLen))
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val resp_rd = Reg(io.resp.bits.rd)
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val addr_block = addr(coreMaxAddrBits - 1, blockOffset)
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val offset = addr(blockOffset - 1, 0)
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val next_addr = (addr_block + UInt(1)) << UInt(blockOffset)
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val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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val gnt = io.dmem.head.grant.bits
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val recv_data = Reg(UInt(width = tlDataBits))
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val recv_beat = Reg(UInt(width = tlBeatAddrBits))
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val data_bytes = Vec.tabulate(tlDataBytes) { i => recv_data(8 * (i + 1) - 1, 8 * i) }
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val zero_match = data_bytes.map(_ === UInt(0))
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val needle_match = data_bytes.map(_ === needle)
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val first_zero = PriorityEncoder(zero_match)
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val chars_found = PopCount(needle_match.zipWithIndex.map {
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case (matches, i) =>
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val idx = Cat(recv_beat, UInt(i, tlByteAddrBits))
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matches && idx >= offset && UInt(i) <= first_zero
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})
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val zero_found = zero_match.reduce(_ || _)
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val finished = Reg(Bool())
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io.cmd.ready := (state === s_idle)
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io.resp.valid := (state === s_resp)
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io.resp.bits.rd := resp_rd
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io.resp.bits.data := count
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io.dmem.head.acquire.valid := (state === s_acq)
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io.dmem.head.acquire.bits := GetBlock(addr_block = addr_block)
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io.dmem.head.grant.ready := (state === s_gnt)
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when (io.cmd.fire()) {
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addr := io.cmd.bits.rs1
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needle := io.cmd.bits.rs2
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resp_rd := io.cmd.bits.inst.rd
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count := UInt(0)
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finished := Bool(false)
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state := s_acq
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}
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when (io.dmem.head.acquire.fire()) { state := s_gnt }
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when (io.dmem.head.grant.fire()) {
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recv_beat := gnt.addr_beat
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recv_data := gnt.data
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state := s_check
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}
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when (state === s_check) {
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when (!finished) {
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count := count + chars_found
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}
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when (zero_found) { finished := Bool(true) }
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when (recv_beat === UInt(tlDataBeats - 1)) {
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addr := next_addr
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state := Mux(zero_found || finished, s_resp, s_acq)
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} .otherwise {
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state := s_gnt
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}
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}
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|
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when (io.resp.fire()) { state := s_idle }
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io.busy := (state =/= s_idle)
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io.interrupt := Bool(false)
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io.mem.req.valid := Bool(false)
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io.imem.acquire.valid := Bool(false)
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io.imem.grant.ready := Bool(false)
|
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io.dptw.req.valid := Bool(false)
|
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io.iptw.req.valid := Bool(false)
|
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io.pptw.req.valid := Bool(false)
|
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}
|
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|
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class OpcodeSet(val opcodes: Seq[UInt]) {
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def |(set: OpcodeSet) =
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new OpcodeSet(this.opcodes ++ set.opcodes)
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def matches(oc: UInt) = opcodes.map(_ === oc).reduce(_ || _)
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}
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|
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object OpcodeSet {
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val custom0 = new OpcodeSet(Seq(Bits("b0001011")))
|
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val custom1 = new OpcodeSet(Seq(Bits("b0101011")))
|
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val custom2 = new OpcodeSet(Seq(Bits("b1011011")))
|
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val custom3 = new OpcodeSet(Seq(Bits("b1111011")))
|
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val all = custom0 | custom1 | custom2 | custom3
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}
|
||||
|
||||
class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters)
|
||||
extends CoreModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = Decoupled(new RoCCCommand).flip
|
||||
val out = Vec(opcodes.size, Decoupled(new RoCCCommand))
|
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val busy = Bool(OUTPUT)
|
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}
|
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|
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val cmd = Queue(io.in)
|
||||
val cmdReadys = io.out.zip(opcodes).map { case (out, opcode) =>
|
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val me = opcode.matches(cmd.bits.inst.opcode)
|
||||
out.valid := cmd.valid && me
|
||||
out.bits := cmd.bits
|
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out.ready && me
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}
|
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cmd.ready := cmdReadys.reduce(_ || _)
|
||||
io.busy := cmd.valid
|
||||
|
||||
assert(PopCount(cmdReadys) <= UInt(1),
|
||||
"Custom opcode matched for more than one accelerator")
|
||||
}
|
||||
|
|
|
|||
|
|
@ -60,6 +60,47 @@ abstract class CoreModule(implicit val p: Parameters) extends Module
|
|||
abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
|
||||
with HasCoreParameters
|
||||
|
||||
class RegFile(n: Int, w: Int, zero: Boolean = false) {
|
||||
private val rf = Mem(n, UInt(width = w))
|
||||
private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0))
|
||||
private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
|
||||
private var canRead = true
|
||||
def read(addr: UInt) = {
|
||||
require(canRead)
|
||||
reads += addr -> Wire(UInt())
|
||||
reads.last._2 := Mux(Bool(zero) && addr === UInt(0), UInt(0), access(addr))
|
||||
reads.last._2
|
||||
}
|
||||
def write(addr: UInt, data: UInt) = {
|
||||
canRead = false
|
||||
when (addr != UInt(0)) {
|
||||
access(addr) := data
|
||||
for ((raddr, rdata) <- reads)
|
||||
when (addr === raddr) { rdata := data }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
object ImmGen {
|
||||
def apply(sel: UInt, inst: UInt) = {
|
||||
val sign = Mux(sel === IMM_Z, SInt(0), inst(31).toSInt)
|
||||
val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign)
|
||||
val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, inst(19,12).toSInt)
|
||||
val b11 = Mux(sel === IMM_U || sel === IMM_Z, SInt(0),
|
||||
Mux(sel === IMM_UJ, inst(20).toSInt,
|
||||
Mux(sel === IMM_SB, inst(7).toSInt, sign)))
|
||||
val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, Bits(0), inst(30,25))
|
||||
val b4_1 = Mux(sel === IMM_U, Bits(0),
|
||||
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
|
||||
Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
|
||||
val b0 = Mux(sel === IMM_S, inst(7),
|
||||
Mux(sel === IMM_I, inst(20),
|
||||
Mux(sel === IMM_Z, inst(15), Bits(0))))
|
||||
|
||||
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt
|
||||
}
|
||||
}
|
||||
|
||||
class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
||||
val io = new Bundle {
|
||||
val host = new HtifIO
|
||||
|
|
@ -131,7 +172,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
val id_reg_fence = Reg(init=Bool(false))
|
||||
val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)
|
||||
val id_raddr = IndexedSeq(id_raddr1, id_raddr2)
|
||||
val rf = new RegFile
|
||||
val rf = new RegFile(31, xLen)
|
||||
val id_rs = id_raddr.map(rf.read _)
|
||||
val ctrl_killd = Wire(Bool())
|
||||
|
||||
|
|
@ -189,7 +230,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
val ex_reg_rs_msb = Reg(Vec(UInt(), id_raddr.size))
|
||||
val ex_rs = for (i <- 0 until id_raddr.size)
|
||||
yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
|
||||
val ex_imm = imm(ex_ctrl.sel_imm, ex_reg_inst)
|
||||
val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst)
|
||||
val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, SInt(0), Seq(
|
||||
A1_RS1 -> ex_rs(0).toSInt,
|
||||
A1_PC -> ex_reg_pc.toSInt))
|
||||
|
|
@ -261,8 +302,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
// memory stage
|
||||
val mem_br_taken = mem_reg_wdata(0)
|
||||
val mem_br_target = mem_reg_pc.toSInt +
|
||||
Mux(mem_ctrl.branch && mem_br_taken, imm(IMM_SB, mem_reg_inst),
|
||||
Mux(mem_ctrl.jal, imm(IMM_UJ, mem_reg_inst), SInt(4)))
|
||||
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
|
||||
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), SInt(4)))
|
||||
val mem_int_wdata = Mux(mem_ctrl.jalr, mem_br_target, mem_reg_wdata.toSInt).toUInt
|
||||
val mem_npc = (Mux(mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)).toSInt, mem_br_target) & SInt(-2)).toUInt
|
||||
val mem_wrong_npc = mem_npc != ex_reg_pc || !ex_reg_valid
|
||||
|
|
@ -323,8 +364,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
}
|
||||
|
||||
val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc
|
||||
val replay_wb_common =
|
||||
io.dmem.resp.bits.nack || wb_reg_replay || csr.io.csr_replay
|
||||
val replay_wb_common = io.dmem.resp.bits.nack || wb_reg_replay
|
||||
val wb_rocc_val = wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
|
||||
val replay_wb = replay_wb_common || wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
|
||||
val wb_xcpt = wb_reg_xcpt || csr.io.csr_xcpt
|
||||
|
|
@ -548,24 +588,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
|
||||
targets.map(h => h._1 && cond(h._2)).reduce(_||_)
|
||||
|
||||
def imm(sel: UInt, inst: UInt) = {
|
||||
val sign = Mux(sel === IMM_Z, SInt(0), inst(31).toSInt)
|
||||
val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign)
|
||||
val b19_12 = Mux(sel != IMM_U && sel != IMM_UJ, sign, inst(19,12).toSInt)
|
||||
val b11 = Mux(sel === IMM_U || sel === IMM_Z, SInt(0),
|
||||
Mux(sel === IMM_UJ, inst(20).toSInt,
|
||||
Mux(sel === IMM_SB, inst(7).toSInt, sign)))
|
||||
val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, Bits(0), inst(30,25))
|
||||
val b4_1 = Mux(sel === IMM_U, Bits(0),
|
||||
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
|
||||
Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
|
||||
val b0 = Mux(sel === IMM_S, inst(7),
|
||||
Mux(sel === IMM_I, inst(20),
|
||||
Mux(sel === IMM_Z, inst(15), Bits(0))))
|
||||
|
||||
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt
|
||||
}
|
||||
|
||||
def vaSign(a0: UInt, ea: UInt) = {
|
||||
// efficient means to compress 64-bit VA into vaddrBits+1 bits
|
||||
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
|
||||
|
|
@ -576,26 +598,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
|||
e(0)))
|
||||
}
|
||||
|
||||
class RegFile {
|
||||
private val rf = Mem(31, UInt(width = 64))
|
||||
private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
|
||||
private var canRead = true
|
||||
def read(addr: UInt) = {
|
||||
require(canRead)
|
||||
reads += addr -> Wire(UInt())
|
||||
reads.last._2 := rf(~addr)
|
||||
reads.last._2
|
||||
}
|
||||
def write(addr: UInt, data: UInt) = {
|
||||
canRead = false
|
||||
when (addr != UInt(0)) {
|
||||
rf(~addr) := data
|
||||
for ((raddr, rdata) <- reads)
|
||||
when (addr === raddr) { rdata := data }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class Scoreboard(n: Int)
|
||||
{
|
||||
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
|
||||
|
|
|
|||
|
|
@ -8,15 +8,21 @@ import Util._
|
|||
import cde.{Parameters, Field}
|
||||
|
||||
case object CoreName extends Field[String]
|
||||
case object BuildRoCC extends Field[Option[Parameters => RoCC]]
|
||||
case object BuildRoCC extends Field[Seq[Parameters => RoCC]]
|
||||
case object RoccOpcodes extends Field[Seq[OpcodeSet]]
|
||||
case object RoccAcceleratorMemChannels extends Field[Seq[Int]]
|
||||
|
||||
abstract class Tile(resetSignal: Bool = null)
|
||||
(implicit p: Parameters) extends Module(_reset = resetSignal) {
|
||||
val usingRocc = !p(BuildRoCC).isEmpty
|
||||
val nDCachePorts = 2 + (if(!usingRocc) 0 else 1)
|
||||
val nPTWPorts = 2 + (if(!usingRocc) 0 else 3)
|
||||
val buildRocc = p(BuildRoCC)
|
||||
val roccOpcodes = p(RoccOpcodes)
|
||||
val roccMemChannels = p(RoccAcceleratorMemChannels)
|
||||
val usingRocc = !buildRocc.isEmpty
|
||||
val nRocc = buildRocc.size
|
||||
val nDCachePorts = 2 + nRocc
|
||||
val nPTWPorts = 2 + 3 * nRocc
|
||||
val nCachedTileLinkPorts = 1
|
||||
val nUncachedTileLinkPorts = 1 + (if(!usingRocc) 0 else p(RoccNMemChannels))
|
||||
val nUncachedTileLinkPorts = 1 + p(RoccNMemChannels)
|
||||
val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
|
||||
val io = new Bundle {
|
||||
val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
|
||||
|
|
@ -53,18 +59,37 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
|
|||
io.cached.head <> dcache.io.mem
|
||||
// If so specified, build an RoCC module and wire it to core + TileLink ports,
|
||||
// otherwise just hookup the icache
|
||||
io.uncached <> p(BuildRoCC).map { buildItHere =>
|
||||
val rocc = buildItHere(p)
|
||||
val iMemArb = Module(new ClientTileLinkIOArbiter(2))
|
||||
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
|
||||
core.io.rocc <> rocc.io
|
||||
dcIF.io.requestor <> rocc.io.mem
|
||||
dcArb.io.requestor(2) <> dcIF.io.cache
|
||||
io.uncached <> (if (usingRocc) {
|
||||
val iMemArb = Module(new ClientTileLinkIOArbiter(1 + nRocc))
|
||||
iMemArb.io.in(0) <> icache.io.mem
|
||||
iMemArb.io.in(1) <> rocc.io.imem
|
||||
ptw.io.requestor(2) <> rocc.io.iptw
|
||||
ptw.io.requestor(3) <> rocc.io.dptw
|
||||
ptw.io.requestor(4) <> rocc.io.pptw
|
||||
rocc.io.dmem :+ iMemArb.io.out
|
||||
}.getOrElse(List(icache.io.mem))
|
||||
|
||||
val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
|
||||
core.io.rocc.resp <> respArb.io.out
|
||||
|
||||
val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
|
||||
cmdRouter.io.in <> core.io.rocc.cmd
|
||||
|
||||
val roccs = buildRocc.zip(roccMemChannels).zipWithIndex.map {
|
||||
case ((buildItHere, nchannels), i) =>
|
||||
val accelParams = p.alterPartial({ case RoccNMemChannels => nchannels})
|
||||
val rocc = buildItHere(accelParams)
|
||||
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
|
||||
rocc.io.cmd <> cmdRouter.io.out(i)
|
||||
rocc.io.s := core.io.rocc.s
|
||||
rocc.io.exception := core.io.rocc.exception
|
||||
dcIF.io.requestor <> rocc.io.mem
|
||||
dcArb.io.requestor(2 + i) <> dcIF.io.cache
|
||||
iMemArb.io.in(1 + i) <> rocc.io.imem
|
||||
ptw.io.requestor(2 + 3 * i) <> rocc.io.iptw
|
||||
ptw.io.requestor(3 + 3 * i) <> rocc.io.dptw
|
||||
ptw.io.requestor(4 + 3 * i) <> rocc.io.pptw
|
||||
rocc
|
||||
}
|
||||
|
||||
core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
|
||||
core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
|
||||
respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
|
||||
|
||||
roccs.flatMap(_.io.dmem) :+ iMemArb.io.out
|
||||
} else { Seq(icache.io.mem) })
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user