do all the writes before doing the gets in GeneratorTest
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@ -41,7 +41,7 @@ class UncachedTileLinkGenerator(id: Int)
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val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val (req_cnt, req_wrap) = Counter(io.mem.grant.fire() && state === s_get, maxRequests)
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val (req_cnt, req_wrap) = Counter(io.mem.grant.fire(), maxRequests)
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val sending = Reg(init = Bool(false))
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@ -50,18 +50,9 @@ class UncachedTileLinkGenerator(id: Int)
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state := s_put
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}
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when (state === s_put) {
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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when (io.mem.grant.fire()) { sending := Bool(true); state := s_get }
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}
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when (state === s_get) {
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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when (io.mem.grant.fire()) {
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sending := Bool(true)
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state := Mux(req_wrap, s_finished, s_put)
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}
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}
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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when (io.mem.grant.fire()) { sending := Bool(true) }
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when (req_wrap) { state := Mux(state === s_put, s_get, s_finished) }
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val timeout = Timer(genTimeout, io.mem.acquire.fire(), io.mem.grant.fire())
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assert(!timeout, s"Uncached generator ${id} timed out waiting for grant")
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@ -73,8 +64,6 @@ class UncachedTileLinkGenerator(id: Int)
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(if (genCached) UInt(0, 1) else UInt(0, 0)),
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UInt(0, wordOffset))
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when (io.mem.acquire.fire()) { printf("Uncached sending %x\n", full_addr) }
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val addr_block = full_addr >> UInt(tlBlockOffset)
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val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits)
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val addr_byte = full_addr(tlByteAddrBits - 1, 0)
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@ -102,9 +91,9 @@ class UncachedTileLinkGenerator(id: Int)
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operand_size = MT_D,
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alloc = Bool(false))
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io.mem.acquire.valid := sending
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io.mem.acquire.valid := sending && !io.finished
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.mem.grant.ready := !sending
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io.mem.grant.ready := !sending && !io.finished
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def wordFromBeat(addr: UInt, dat: UInt) = {
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val offset = addr(tlByteAddrBits - 1, wordOffset)
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@ -131,8 +120,7 @@ class HellaCacheGenerator(id: Int)
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val state = Reg(init = s_start)
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val sending = Reg(init = Bool(false))
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val (req_cnt, req_wrap) = Counter(
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io.mem.resp.valid && io.mem.resp.bits.has_data, maxRequests)
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val (req_cnt, req_wrap) = Counter(io.mem.resp.valid, maxRequests)
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val req_addr = UInt(startAddress) + Cat(
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req_cnt, UInt(id, log2Ceil(nGens)),
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@ -140,7 +128,7 @@ class HellaCacheGenerator(id: Int)
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UInt(0, wordOffset))
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val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, req_addr)
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io.mem.req.valid := sending
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io.mem.req.valid := sending && !io.finished
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io.mem.req.bits.addr := req_addr
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io.mem.req.bits.data := req_data
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io.mem.req.bits.typ := MT_D
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@ -152,13 +140,9 @@ class HellaCacheGenerator(id: Int)
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when (state === s_start) { sending := Bool(true); state := s_write }
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when (io.mem.req.fire()) { sending := Bool(false) }
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when (io.mem.resp.valid) { sending := Bool(true) }
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when (io.mem.resp.valid) {
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sending := Bool(true)
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state := Mux(state === s_write, s_read, s_write)
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}
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when (req_wrap) { sending := Bool(false); state := s_finished }
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when (req_wrap) { state := Mux(state === s_write, s_read, s_finished) }
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io.finished := (state === s_finished)
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