riscv/rocket-chip
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use implicit parameters for ALU

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This commit is contained in:
Howard Mao 2015-11-30 17:35:33 -08:00
parent 90991014a0
commit e80340198a
2 changed files with 2 additions and 2 deletions
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2
rocket/src/main/scala/dpath_alu.scala
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@ -43,7 +43,7 @@ object ALU
}
import ALU._
class ALU(xLen: Int) extends Module {
class ALU(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val dw = Bits(INPUT, SZ_DW)
val fn = Bits(INPUT, SZ_ALU_FN)

2
rocket/src/main/scala/rocket.scala
View File

@ -239,7 +239,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
A2_IMM -> ex_imm,
A2_FOUR -> SInt(4)))
val alu = Module(new ALU(xLen))
val alu = Module(new ALU)
alu.io.dw := ex_ctrl.alu_dw
alu.io.fn := ex_ctrl.alu_fn
alu.io.in2 := ex_op2.toUInt