add a regression to test proper writeback
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@ -312,6 +312,62 @@ class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression()
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"SequentialSameIdGetRegression: grant received out of order")
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}
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/* Test that a writeback will occur by writing nWays + 1 blocks to the same
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* set. This assumes that there is only a single cache bank. If we want to
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* test multibank configurations, we'll have to think of some other way to
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* determine which banks are conflicting */
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class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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val l2params = p.alterPartial({ case CacheName => "L2Bank" })
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val nSets = l2params(NSets)
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val nWays = l2params(NWays)
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val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(i * nSets) }
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val data = Vec.tabulate(nWays + 1) { i => UInt((i + 1) * 1423) }
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val (put_beat, put_done) = Counter(
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io.mem.acquire.fire() && io.mem.acquire.bits.hasData(), tlDataBeats)
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val (get_beat, get_done) = Counter(
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io.mem.grant.fire() && io.mem.grant.bits.hasData(), tlDataBeats)
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val (put_cnt, _) = Counter(put_done, nWays + 1)
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val (get_cnt, _) = Counter(
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io.mem.acquire.fire() && !io.mem.acquire.bits.hasData(), nWays + 1)
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val (ack_cnt, ack_done) = Counter(
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io.mem.grant.fire() && !io.mem.grant.bits.hasData() || get_done, nWays + 1)
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val s_idle :: s_put :: s_get :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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val sending = Reg(init = Bool(false))
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := Mux(state === s_put,
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PutBlock(
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client_xact_id = UInt(0),
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addr_block = addr_blocks(put_cnt),
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addr_beat = put_beat,
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data = data(put_cnt)),
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GetBlock(
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client_xact_id = UInt(0),
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addr_block = addr_blocks(get_cnt)))
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io.mem.grant.ready := !sending
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when (state === s_idle && io.start) { state := s_put; sending := Bool(true) }
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when (put_done || state === s_get && io.mem.acquire.fire()) {
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sending := Bool(false)
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}
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when (get_done && !ack_done || state === s_put && io.mem.grant.fire()) {
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sending := Bool(true)
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}
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when (ack_done) { state := Mux(state === s_put, s_get, s_done) }
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io.finished := (state === s_done)
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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io.mem.grant.bits.data === data(ack_cnt),
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"WritebackRegression: incorrect data")
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}
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object RegressionTests {
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def cacheRegressions(implicit p: Parameters) = Seq(
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Module(new PutBlockMergeRegression),
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@ -319,10 +375,12 @@ object RegressionTests {
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Module(new RepeatedNoAllocPutRegression),
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Module(new WriteMaskedPutBlockRegression),
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Module(new PrefetchHitRegression),
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Module(new SequentialSameIdGetRegression))
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Module(new SequentialSameIdGetRegression),
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Module(new WritebackRegression))
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def broadcastRegressions(implicit p: Parameters) = Seq(
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Module(new IOGetAfterPutBlockRegression),
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Module(new WriteMaskedPutBlockRegression))
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Module(new WriteMaskedPutBlockRegression),
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Module(new SequentialSameIdGetRegression))
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}
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case object GroundTestRegressions extends Field[Parameters => Seq[Regression]]
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