Merge branch 'master' into rocc-fpu-port
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commit
65632c875a
@ -1079,7 +1079,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
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val cache = new HellaCacheIO
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}
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val replaying_cmb = Bool()
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val replaying_cmb = Wire(Bool())
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val replaying = Reg(next = replaying_cmb, init = Bool(false))
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replaying_cmb := replaying
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@ -1099,10 +1099,10 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
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val s1_req_fire = Reg(next=s0_req_fire)
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val s2_req_fire = Reg(next=s1_req_fire)
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io.cache.req <> req_arb.io.out
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io.cache.req.bits.kill := s2_nack
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io.cache.req.bits.phys := Bool(true)
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io.cache.req.bits.data := RegEnable(req_arb.io.out.bits.data, s0_req_fire)
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io.cache.req <> req_arb.io.out
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/* replay queues:
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replayq1 holds the older request.
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