add DMA test
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4858ca9a60
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@ -4,7 +4,7 @@ import Chisel._
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import uncore._
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import cde.{Parameters, Field}
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class CacheFillTest(implicit val p: Parameters) extends GroundTest()(p)
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class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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with HasTileLinkParameters {
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val capacityKb: Int = p("L2_CAPACITY_IN_KB")
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val nblocks = capacityKb * 1024 / p(CacheBlockBytes)
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@ -14,6 +14,8 @@ class CacheFillTest(implicit val p: Parameters) extends GroundTest()(p)
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val inflight = Reg(init = Bool(false))
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val active = state === s_prefetch || state === s_retrieve
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disablePorts(mem = false)
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val (xact_id, xact_flip) = Counter(io.mem.acquire.fire(), tlMaxClientXacts)
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val (req_block, round_done) = Counter(io.mem.acquire.fire(), nblocks)
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@ -39,5 +41,4 @@ class CacheFillTest(implicit val p: Parameters) extends GroundTest()(p)
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when (state === s_retrieve && round_done) { state := s_finished }
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io.finished := (state === s_finished)
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io.cache.req.valid := Bool(false)
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}
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123
groundtest/src/main/scala/dmatest.scala
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123
groundtest/src/main/scala/dmatest.scala
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@ -0,0 +1,123 @@
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package groundtest
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import Chisel._
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import uncore._
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import rocket._
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import junctions.PAddrBits
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import cde.{Parameters, Field}
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case class DmaTestCase(source: Int, dest: Int, length: Int)
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object DmaTestCases {
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def apply(cases: (Int, Int, Int) *): Seq[DmaTestCase] = {
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cases.toSeq.map {
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case (source, dest, length) => DmaTestCase(source, dest, length)
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}
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}
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}
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case object DmaTestSet extends Field[Seq[DmaTestCase]]
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case object DmaTestDataStart extends Field[Int]
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case object DmaTestDataStride extends Field[Int]
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class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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with HasDmaParameters with HasCoreParameters {
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private val testSet = p(DmaTestSet)
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private val dataStart = p(DmaTestDataStart)
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private val dataStride = p(DmaTestDataStride)
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private val wordBits = 32
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private val wordBytes = wordBits / 8
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private val pAddrBits = p(PAddrBits)
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disablePorts(cache = false, dma = false, ptw = false)
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val sourceAddrs = Vec(testSet.map(test => UInt(test.source)))
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val destAddrs = Vec(testSet.map(test => UInt(test.dest)))
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val transferLengths = Vec(testSet.map(test => UInt(test.length)))
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val testIdx = Reg(init = UInt(0, log2Up(testSet.size)))
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val (s_start :: s_fill_req :: s_fill_resp :: s_copy_req :: s_copy_wait ::
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s_check_req :: s_check_resp :: s_finished :: Nil) = Enum(Bits(), 8)
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val state = Reg(init = s_start)
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val req_data = Reg(UInt(width = wordBits))
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val req_addr = Reg(UInt(width = pAddrBits))
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val bytes_left = Reg(UInt(width = pAddrBits))
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val prefetch = sourceAddrs(testIdx) === destAddrs(testIdx)
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val frontend = Module(new DmaFrontend)
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frontend.io.cpu.req.valid := (state === s_copy_req)
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frontend.io.cpu.req.bits := ClientDmaRequest(
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cmd = Mux(prefetch, DmaRequest.DMA_CMD_PFR, DmaRequest.DMA_CMD_COPY),
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src_start = sourceAddrs(testIdx),
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dst_start = destAddrs(testIdx),
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segment_size = transferLengths(testIdx))
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io.dma <> frontend.io.dma
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io.ptw <> frontend.io.ptw
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io.cache.req.valid := (state === s_fill_req) || (state === s_check_req)
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io.cache.req.bits.addr := req_addr
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io.cache.req.bits.data := req_data
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io.cache.req.bits.typ := MT_W
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io.cache.req.bits.cmd := Mux(state === s_fill_req, M_XWR, M_XRD)
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io.cache.req.bits.kill := Bool(false)
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io.cache.req.bits.phys := Bool(false)
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when (state === s_start) {
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req_addr := sourceAddrs(testIdx)
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req_data := UInt(dataStart)
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bytes_left := transferLengths(testIdx)
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state := s_fill_req
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}
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when (io.cache.req.fire()) {
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req_addr := req_addr + UInt(wordBytes)
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bytes_left := bytes_left - UInt(wordBytes)
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state := Mux(state === s_fill_req, s_fill_resp, s_check_resp)
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}
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when (state === s_fill_resp && io.cache.resp.valid) {
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req_data := req_data + UInt(dataStride)
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state := Mux(bytes_left === UInt(0), s_copy_req, s_fill_req)
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}
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when (frontend.io.cpu.req.fire()) { state := s_copy_wait }
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when (state === s_copy_wait && !frontend.io.busy) {
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req_addr := destAddrs(testIdx)
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req_data := UInt(dataStart)
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bytes_left := transferLengths(testIdx)
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state := s_check_req
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}
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when (state === s_check_resp && io.cache.resp.valid) {
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req_data := req_data + UInt(dataStride)
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when (bytes_left > UInt(0)) {
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state := s_check_req
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} .elsewhen (testIdx === UInt(testSet.size - 1)) {
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state := s_finished
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} .otherwise {
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testIdx := testIdx + UInt(1)
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state := s_start
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}
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}
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io.finished := (state === s_finished)
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testSet.foreach { case DmaTestCase(source, dest, length) =>
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require(source % wordBytes == 0, "source address must be word-aligned")
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require(dest % wordBytes == 0, "destination address must be word-aligned")
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require(length % wordBytes == 0, "transfer length must be word-aligned")
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}
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assert(!io.cache.resp.valid || !io.cache.resp.bits.has_data ||
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io.cache.resp.bits.data === req_data, "Received data does not match")
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val dma_timeout = Timer(1000, io.dma.req.fire(), io.dma.resp.fire())
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assert(!dma_timeout, "DMA request timed out")
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val cache_timeout = Timer(1000, io.cache.req.fire(), io.cache.resp.valid)
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assert(!cache_timeout, "Memory request timed out")
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}
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@ -151,28 +151,23 @@ class HellaCacheGenerator(id: Int)
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s"Received incorrect data in cached generator ${id}")
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}
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class GeneratorTest(id: Int)(implicit val p: Parameters)
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class GeneratorTest(id: Int)(implicit p: Parameters)
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extends GroundTest()(p) with HasGeneratorParams {
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val gen_finished = Wire(Vec(2, Bool()))
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disablePorts(mem = !genUncached, cache = !genCached)
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val gen_finished = Wire(init = Vec.fill(2){Bool(true)})
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if (genUncached) {
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val uncacheGen = Module(new UncachedTileLinkGenerator(id))
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io.mem <> uncacheGen.io.mem
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gen_finished(0) := uncacheGen.io.finished
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} else {
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io.mem.acquire.valid := Bool(false)
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io.mem.grant.ready := Bool(false)
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gen_finished(0) := Bool(true)
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}
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if (genCached) {
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val cacheGen = Module(new HellaCacheGenerator(id))
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io.cache <> cacheGen.io.mem
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gen_finished(1) := cacheGen.io.finished
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} else {
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io.cache.req.valid := Bool(false)
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gen_finished(1) := Bool(true)
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}
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io.finished := gen_finished.reduce(_ && _)
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@ -386,6 +386,7 @@ object RegressionTests {
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case object GroundTestRegressions extends Field[Parameters => Seq[Regression]]
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class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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disablePorts(mem = false, cache = false)
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val regressions = p(GroundTestRegressions)(p)
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val regressIOs = Vec(regressions.map(_.io))
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@ -12,8 +12,7 @@ case object GroundTestMaxXacts extends Field[Int]
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/** A "cache" that responds to probe requests with a release indicating
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* the block is not present */
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class DummyCache(implicit val p: Parameters) extends Module
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with HasGeneratorParams {
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class DummyCache(implicit val p: Parameters) extends Module {
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val io = new ClientTileLinkIO
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val req = Reg(new Probe)
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@ -37,6 +36,45 @@ class DummyCache(implicit val p: Parameters) extends Module
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}
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}
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class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestors = Vec(n, new TLBPTWIO).flip
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}
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val req_arb = Module(new RRArbiter(new PTWReq, n))
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req_arb.io.in <> io.requestors.map(_.req)
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req_arb.io.out.ready := Bool(true)
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def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
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class QueueChannel extends ParameterizedBundle()(p) {
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val ppn = UInt(width = ppnBits)
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val chosen = UInt(width = log2Up(n))
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}
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val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
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val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
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val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
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val s2_valid = Reg(next = req_arb.io.out.valid)
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val s2_resp = Wire(new PTWResp)
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s2_resp.error := Bool(false)
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s2_resp.pte.ppn := s2_ppn
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s2_resp.pte.reserved_for_software := UInt(0)
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s2_resp.pte.d := Bool(false)
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s2_resp.pte.r := Bool(false)
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s2_resp.pte.typ := UInt(2)
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s2_resp.pte.v := Bool(true)
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io.requestors.zipWithIndex.foreach { case (requestor, i) =>
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requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
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requestor.resp.bits := s2_resp
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requestor.status.mprv := Bool(false)
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requestor.status.vm := UInt("b01000")
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requestor.status.prv := UInt(PRV_S)
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}
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}
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class CSRHandler(implicit val p: Parameters) extends Module {
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private val csrDataBits = 64
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private val csrAddrBits = 12
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@ -67,20 +105,44 @@ class CSRHandler(implicit val p: Parameters) extends Module {
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class GroundTestIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val cache = new HellaCacheIO
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val mem = new ClientUncachedTileLinkIO
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val dma = new DmaIO
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val ptw = new TLBPTWIO
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val finished = Bool(OUTPUT)
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}
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abstract class GroundTest(implicit p: Parameters) extends Module {
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abstract class GroundTest(implicit val p: Parameters) extends Module {
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val io = new GroundTestIO
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def disablePorts(mem: Boolean = true,
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cache: Boolean = true,
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dma: Boolean = true,
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ptw: Boolean = true) {
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if (mem) {
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io.mem.acquire.valid := Bool(false)
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io.mem.grant.ready := Bool(false)
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}
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if (cache) {
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io.cache.req.valid := Bool(false)
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}
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if (dma) {
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io.dma.req.valid := Bool(false)
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io.dma.resp.ready := Bool(false)
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}
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if (ptw) {
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io.ptw.req.valid := Bool(false)
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}
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}
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}
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class GroundTestTile(id: Int, resetSignal: Bool)
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(implicit val p: Parameters) extends Tile(resetSignal)(p) {
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val dcache = Module(new HellaCache()(dcacheParams))
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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val test = p(BuildGroundTest)(id, dcacheParams)
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io.uncached.head <> test.io.mem
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io.dma <> test.io.dma
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val dcache = Module(new HellaCache()(dcacheParams))
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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dcacheIF.io.requestor <> test.io.cache
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dcache.io.cpu <> dcacheIF.io.cache
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io.cached.head <> dcache.io.mem
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@ -88,4 +150,8 @@ class GroundTestTile(id: Int, resetSignal: Bool)
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val csr = Module(new CSRHandler)
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csr.io.finished := test.io.finished
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csr.io.csr <> io.host.csr
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val ptw = Module(new DummyPTW(2))
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ptw.io.requestors(0) <> test.io.ptw
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ptw.io.requestors(1) <> dcache.io.ptw
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}
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