add some more regression tests
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Howard Mao
parent
484e8ce20b
commit
176d3c890c
@ -3,13 +3,18 @@ package groundtest
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import Chisel._
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import uncore._
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import junctions.{MMIOBase, ParameterizedBundle}
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import cde.Parameters
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import rocket.HellaCacheIO
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import cde.{Parameters, Field}
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class RegressionIO(implicit val p: Parameters) extends GroundTestIO()(p) {
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class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
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val start = Bool(INPUT)
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val cache = new HellaCacheIO
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val mem = new ClientUncachedTileLinkIO
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val finished = Bool(OUTPUT)
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}
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abstract class Regression(implicit val p: Parameters) extends Module {
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abstract class Regression(implicit val p: Parameters)
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extends Module with HasTileLinkParameters {
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val io = new RegressionIO
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}
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@ -19,9 +24,7 @@ abstract class Regression(implicit val p: Parameters) extends Module {
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* same time. Repeating this sequence enough times will cause a queue to
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* get filled up and deadlock the system.
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*/
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class IOGetAfterPutBlockRegression(implicit p: Parameters)
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extends Regression()(p) with HasTileLinkParameters {
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class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(p) {
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val nRuns = 7
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val run = Reg(init = UInt(0, log2Up(nRuns + 1)))
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@ -71,10 +74,262 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters)
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io.finished := (run === UInt(nRuns))
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}
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/* This was a bug with merging two PutBlocks to the same address in the L2.
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* The transactor would start accepting beats of the second transaction but
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* acknowledge both of them when the first one finished.
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* This caused the state to go funky since the next time around it would
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* start the put in the middle */
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class PutBlockMergeRegression(implicit p: Parameters)
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extends Regression()(p) with HasTileLinkParameters {
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val s_idle :: s_put :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.cache.req.valid := Bool(false)
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val l2params = p.alterPartial({ case CacheName => "L2Bank" })
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val nSets = l2params(NSets)
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val addr_blocks = Vec(UInt(0), UInt(0), UInt(nSets))
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val nSteps = addr_blocks.size
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val (acq_beat, acq_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
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val (send_cnt, send_done) = Counter(acq_done, nSteps)
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val (ack_cnt, ack_done) = Counter(io.mem.grant.fire(), nSteps)
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io.mem.acquire.valid := (state === s_put)
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io.mem.acquire.bits := PutBlock(
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client_xact_id = send_cnt,
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addr_block = addr_blocks(send_cnt),
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addr_beat = acq_beat,
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data = Cat(send_cnt, acq_beat))
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io.mem.grant.ready := Bool(true)
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when (state === s_idle && io.start) { state := s_put }
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when (send_done) { state := s_wait }
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when (ack_done) { state := s_done }
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io.finished := (state === s_done)
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}
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/* Make sure the L2 does "the right thing" when a put is sent no-alloc but
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* the block is already in cache. It should just treat the request as a
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* regular allocating put */
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class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
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val (s_idle :: s_prefetch :: s_put :: s_get ::
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s_wait :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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val acq = io.mem.acquire.bits
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val gnt = io.mem.grant.bits
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val (put_beat, put_done) = Counter(io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
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val acked = Reg(init = UInt(0, tlDataBeats + 2))
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val addr_block = UInt(2)
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val test_data = UInt(0x3446)
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val prefetch_acq = GetPrefetch(
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client_xact_id = UInt(0),
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addr_block = addr_block)
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val put_acq = PutBlock(
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client_xact_id = UInt(1),
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addr_block = addr_block,
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addr_beat = put_beat,
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data = test_data,
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alloc = Bool(false))
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val get_acq = GetBlock(
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client_xact_id = UInt(2),
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addr_block = addr_block)
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io.mem.acquire.valid := (state === s_prefetch) || (state === s_get) || (state === s_put)
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io.mem.acquire.bits := MuxBundle(get_acq, Seq(
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(state === s_prefetch) -> prefetch_acq,
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(state === s_put) -> put_acq))
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io.mem.grant.ready := Bool(true)
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when (state === s_idle && io.start) { state := s_prefetch }
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when (state === s_prefetch && io.mem.acquire.ready) { state := s_put }
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when (put_done) { state := s_get }
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when (state === s_get && io.mem.acquire.ready) { state := s_wait }
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when (state === s_wait && acked.andR) { state := s_done }
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when (io.mem.grant.fire()) {
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switch (gnt.client_xact_id) {
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is (UInt(0)) { acked := acked | UInt(1 << tlDataBeats) }
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is (UInt(1)) { acked := acked | UInt(1 << (tlDataBeats + 1)) }
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is (UInt(2)) { acked := acked | UIntToOH(gnt.addr_beat) }
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}
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}
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assert(!io.mem.grant.valid || !gnt.hasData() || gnt.data === test_data,
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"NoAllocPutHitRegression: data does not match")
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io.finished := (state === s_done)
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io.cache.req.valid := Bool(false)
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}
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/* Make sure each no-alloc put triggers a request to outer memory.
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* Unfortunately, there's no way to verify that this works except by looking
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* at the waveform */
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class RepeatedNoAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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val nPuts = 2
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val (put_beat, put_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
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val (req_cnt, req_done) = Counter(put_done, nPuts)
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val sending = Reg(init = Bool(false))
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val acked = Reg(init = UInt(0, nPuts))
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when (!sending && io.start) { sending := Bool(true) }
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when (sending && req_done) { sending := Bool(false) }
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := PutBlock(
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client_xact_id = req_cnt,
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addr_block = UInt(5),
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addr_beat = put_beat,
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data = Cat(req_cnt, UInt(0, 8)),
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alloc = Bool(false))
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io.mem.grant.ready := Bool(true)
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when (io.mem.grant.fire()) {
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acked := acked | UIntToOH(io.mem.grant.bits.client_xact_id)
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}
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io.finished := acked.andR
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}
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/* Make sure write masking works properly.
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* This test assumes the memory is initialized to zero at the beginning.
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* This is true for the test harnesses, but not on the FPGA.
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* Technically, what should be done is to fill up a single set until the
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* first block is evicted, and then do the write-masked puts.
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* But this is annoying, and I doubt we will ever run these regression
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* tests on the FPGA. So ... */
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class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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val s_idle :: s_put :: s_get :: s_wait :: s_done :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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val nPuts = 2
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val (put_beat, put_block_done) = Counter(
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io.mem.acquire.fire() && io.mem.acquire.bits.hasData(), tlDataBeats)
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val (put_cnt, puts_done) = Counter(put_block_done, nPuts)
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val data_bytes = Vec.tabulate(nPuts) { i => UInt(i, 8) }
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val data_beat = Fill(tlDataBytes, data_bytes(put_cnt))
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val acked = Reg(init = UInt(0, nPuts + 1))
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val put_acq = PutBlock(
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client_xact_id = put_cnt,
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addr_block = UInt(7),
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addr_beat = put_beat,
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data = data_beat,
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wmask = UIntToOH(put_cnt))
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val get_acq = Get(
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client_xact_id = UInt(nPuts),
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addr_block = UInt(7),
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addr_beat = UInt(0),
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addr_byte = UInt(0),
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operand_size = MT_D,
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alloc = Bool(false))
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io.mem.acquire.valid := (state === s_put || state === s_get)
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io.mem.acquire.bits := Mux(state === s_get, get_acq, put_acq)
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io.mem.grant.ready := Bool(true)
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when (io.mem.grant.fire()) {
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acked := acked | UIntToOH(io.mem.grant.bits.client_xact_id)
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}
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when (state === s_idle && io.start) { state := s_put }
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when (puts_done) { state := s_get }
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when (state === s_get && io.mem.acquire.ready) { state := s_wait }
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when (state === s_wait && acked.andR) { state := s_done }
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io.finished := (state === s_done)
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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io.mem.grant.bits.data === data_bytes.toBits,
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"WriteMaskedPutBlockRegression: data does not match")
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}
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/* Make sure a prefetch that hits returns immediately. */
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class PrefetchHitRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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val sending = Reg(init = Bool(false))
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val nPrefetches = 2
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val (pf_cnt, pf_done) = Counter(io.mem.acquire.fire(), nPrefetches)
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val acked = Reg(init = UInt(0, nPrefetches))
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val acq_bits = Vec(
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PutPrefetch(client_xact_id = UInt(0), addr_block = UInt(12)),
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GetPrefetch(client_xact_id = UInt(1), addr_block = UInt(12)))
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := acq_bits(pf_cnt)
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io.mem.grant.ready := Bool(true)
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when (io.mem.grant.fire()) {
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acked := acked | UIntToOH(io.mem.grant.bits.client_xact_id)
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}
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when (!sending && io.start) { sending := Bool(true) }
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when (sending && pf_done) { sending := Bool(false) }
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io.finished := acked.andR
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}
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/* This tests the sort of access the pattern that Hwacha uses.
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* Instead of using PutBlock/GetBlock, it uses word-sized puts and gets.
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* Each request has the same client_xact_id, but there are multiple in flight.
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* The responses therefore must come back in the order they are sent. */
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class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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val sending = Reg(init = Bool(false))
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val finished = Reg(init = Bool(false))
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val (send_cnt, send_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
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val (recv_cnt, recv_done) = Counter(io.mem.grant.fire(), tlDataBeats)
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when (!sending && io.start) { sending := Bool(true) }
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when (send_done) { sending := Bool(false) }
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when (recv_done) { finished := Bool(true) }
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := Get(
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client_xact_id = UInt(0),
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addr_block = UInt(9),
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addr_beat = send_cnt)
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io.mem.grant.ready := !finished
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io.finished := finished
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assert(!io.mem.grant.valid || io.mem.grant.bits.addr_beat === recv_cnt,
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"SequentialSameIdGetRegression: grant received out of order")
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}
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object RegressionTests {
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def cacheRegressions(implicit p: Parameters) = Seq(
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Module(new PutBlockMergeRegression),
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Module(new NoAllocPutHitRegression),
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Module(new RepeatedNoAllocPutRegression),
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Module(new WriteMaskedPutBlockRegression),
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Module(new PrefetchHitRegression),
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Module(new SequentialSameIdGetRegression))
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def broadcastRegressions(implicit p: Parameters) = Seq(
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Module(new IOGetAfterPutBlockRegression),
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Module(new WriteMaskedPutBlockRegression))
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}
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case object GroundTestRegressions extends Field[Parameters => Seq[Regression]]
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class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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val regressions = Seq(
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Module(new IOGetAfterPutBlockRegression))
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val regressions = p(GroundTestRegressions)(p)
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val regressIOs = Vec(regressions.map(_.io))
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val regress_idx = Reg(init = UInt(0, log2Up(regressions.size + 1)))
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val all_done = (regress_idx === UInt(regressions.size))
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@ -112,4 +367,6 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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val timeout = Timer(5000, start, cur_regression.finished)
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assert(!timeout, "Regression timed out")
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assert(!(all_done && io.mem.grant.valid), "Getting grant after test completion")
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}
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