Howard Mao
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428
allow NastiConverterTest and Memtest to run simultaneously
2016-07-08 13:40:52 -07:00
Howard Mao
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
Howard Mao
eeac405ef8
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
2016-07-08 09:33:07 -07:00
Howard Mao
8aa73915a1
put locking arbiter back into converter
2016-07-08 09:31:33 -07:00
Howard Mao
a50ba39ea7
Revert "add buffering and locking to TL -> Nasti converter"
...
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.
Conflicts:
src/main/scala/converters/Nasti.scala
2016-07-08 09:31:33 -07:00
Andrew Waterman
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
Andrew Waterman
70b677ecda
Vec considered harmful; use isOneOf instead ( #64 )
...
Vec is heavyweight and really should only be used for I/O and
dynamic indexing. A recurring pattern in uncore is
Vec(const1, const2, const3) contains x
which is nice but has a deleterious effect on simulation copilation
and execution time. This patch proposes an alternative:
x isOneOf (const1, const2, const3)
x isOneOf seqOfThings
I think it's also more idiomatic.
This is just a prototype; I'm not wed to the name or implementation.
2016-07-07 19:25:57 -07:00
Howard Mao
16a6b11081
fix bug in AXI -> TL converter
2016-07-07 14:34:24 -07:00
Howard Mao
7cc64011fb
simplify amo_mask generation
2016-07-07 12:14:45 -07:00
Howard Mao
1c5e7be75b
make sure Nasti write channel id is set correctly
2016-07-07 12:14:02 -07:00
Howard Mao
8ccc50a8f0
fix IdMapper and TL -> NASTI converter
2016-07-07 10:16:44 -07:00
Howard Mao
8c13e78ab5
add buffering and locking to TL -> AXI converter
2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885
fix voluntary release issue in L2 cache
2016-07-06 16:57:01 -07:00
Howard Mao
5d8d5e598b
add buffering and locking to TL -> Nasti converter
2016-07-06 16:51:45 -07:00
Howard Mao
b10d306b4a
add option to log L2 cache transactions for easier debugging
2016-07-06 14:59:09 -07:00
Howard Mao
64afc795fd
make sure voluntary releases don't get allocated to L2WritebackUnit
2016-07-06 14:10:45 -07:00
Andrew Waterman
2a146155fc
Update to new priv-1.9 PTE format
2016-07-06 10:15:59 -07:00
Howard Mao
f79a3285fb
fix TraceGen and Nasti -> TL converter
2016-07-05 17:42:57 -07:00
Howard Mao
b105076996
fix ID mapper to disallow two in-flight requests with the same inner ID
2016-07-05 17:41:46 -07:00
Howard Mao
af76837970
conform to new NastiWriteDataChannel interface
2016-07-05 17:41:46 -07:00
Albert Ou
4c07aedfad
Rewrite BRAMSlave to infer a single BRAM instance
2016-07-05 14:21:21 -07:00
Howard Mao
c924ec2a22
fixing bufferless broadcast hub
2016-07-05 12:10:22 -07:00
Howard Mao
702444709a
make sure pending bits updated for all releases
2016-07-05 12:08:22 -07:00
Howard Mao
06ed9c5794
add a single-entry queue in front of acquire and release for bufferless broadcast hub
2016-07-05 12:08:22 -07:00
Howard Mao
67bac383e3
hopefully fixed last bugs in Bufferless
2016-07-05 12:08:22 -07:00
Howard Mao
a35388bc27
fix merging of same xact ID puts/gets
2016-07-05 12:08:22 -07:00
Howard Mao
51f7bf1511
fix Bufferless voluntary release issue
2016-07-05 12:08:22 -07:00
Howard Mao
afc51c4a35
make sure TL -> NASTI converter handles multibeat transactions properly
2016-07-05 12:08:22 -07:00
Andrew Waterman
85808f8cbb
Clean up PseudoLRU code
2016-07-02 15:09:12 -07:00
Howard Mao
af51b6f363
bump groundtest and uncore
2016-07-01 18:13:46 -07:00
Howard Mao
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
Howard Mao
caa9ca24b9
NASTI -> TL converter also uses ID mapper
2016-07-01 18:11:29 -07:00
Wesley W. Terpstra
39bee5198d
Nasti Puts: decode wmask to determine addr_byte() and op_size()
...
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
2016-07-01 16:49:32 -07:00
Howard Mao
e163a23583
fix another bug in Widener
2016-07-01 16:24:48 -07:00
Howard Mao
10a46a36ae
fix full_addr() function in TileLink
2016-07-01 15:17:41 -07:00
Howard Mao
e04e3d2571
make TestBench generator handle different top module names
2016-07-01 10:53:08 -07:00
Howard Mao
61e3e5b45a
more WIP on fixing Bufferless
2016-06-30 18:29:51 -07:00
Howard Mao
0eedffa82f
WIP: Fix BufferlessBroadcastHub
2016-06-30 18:29:51 -07:00
Howard Mao
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
Howard Mao
ce46f523c9
make sure Widener uses proper parameters to generate acquire/grant
2016-06-30 18:17:16 -07:00
Howard Mao
a0b1772404
change TileLinkWidthAdapter interface
2016-06-30 15:50:23 -07:00
Howard Mao
39ec927a3f
replace complicated pattern substitutions with automatic variable
2016-06-28 18:30:11 -07:00
Howard Mao
a39a0c0ec4
.prm is output of chisel stage, not firrtl stage
2016-06-28 17:34:37 -07:00
Howard Mao
b30e0254ee
fix Makefrag to detect all Chisel source files
2016-06-28 16:39:10 -07:00
Howard Mao
ebef4ddad0
remove mention of HTIF from README
2016-06-28 15:23:32 -07:00
Andrew Waterman
f1cbb2ff77
Turn up optimization for Verilator compilation
2016-06-28 14:12:46 -07:00
Howard Mao
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
Howard Mao
9feca99d5d
make PutBlock wmask argument match Put
2016-06-28 13:10:46 -07:00
Howard Mao
b936aa9826
refactor uncore files into separate packages
2016-06-28 13:10:46 -07:00