riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
4346111d2a fix remaining vsim harness typo 2015-10-19 20:20:14 -07:00
Howard Mao
896aa892d1 bump uncore for TL -> NASTI converter fix 2015-10-19 15:31:59 -07:00
Howard Mao
d12403e7dc fix up and simplify TL -> NASTI converter logic 2015-10-19 13:47:13 -07:00
Henry Cook
8c3370c2e3 L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale) 2015-10-16 19:15:47 -07:00
Henry Cook
d391f97953 Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU. 2015-10-16 19:11:06 -07:00
Henry Cook
e1f573918d simplify TileLinkParameters with Option 2015-10-16 18:24:38 -07:00
Howard Mao
49667aa4b0 make sure broadcast acquire tracker doesn't try to send requests back-to-back 2015-10-14 18:56:13 -07:00
Howard Mao
c4117eb9a2 make sure TL parameters change properly throughout 
* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
 2015-10-14 18:03:39 -07:00
Howard Mao
1d362d6d3a make sure correct parameters are used for TileLink constructors 2015-10-14 17:58:54 -07:00
Henry Cook
4270fd78a5 Merge branch 'param-refactor-tl' 2015-10-14 12:16:22 -07:00
Henry Cook
7fa3eb95e3 refactor tilelink params 2015-10-14 12:13:37 -07:00
Henry Cook
66ea39638e GlobalAddrMap 2015-10-14 00:23:28 -07:00
Henry Cook
31be6407ec Removed all traces of params 2015-10-14 00:23:28 -07:00
Henry Cook
908922c1a4 refactor NASTI to not use param 2015-10-14 00:23:28 -07:00
Henry Cook
dd5052888d refactor tilelink params, compiles but ExampleSmallConfig fails 2015-10-13 23:44:05 -07:00
Howard Mao
47da284e56 TileLinkNarrower should do nothing if interfaces are the same width 2015-10-13 13:28:47 -07:00
Howard Mao
a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Howard Mao
83df05cb6a add TileLink data narrower 2015-10-13 12:45:39 -07:00
Howard Mao
993ed86198 move ReorderQueue to utils.scala 2015-10-13 09:49:22 -07:00
Henry Cook
9d11b64c75 added HasAddrMapParameters and GlobalAddrMap 2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1 inject params at top-level for MemDessert 2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57 Removed all traces of params 2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3 refactor MemIO to not use params 2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907 refactor NASTI to not use param; new AddrMap class 2015-10-06 11:41:47 -07:00
Andrew Waterman
c2ad0b7dd4 Unfuck fpga-zynq submodule pointer 
Sorry, Scott.
 2015-10-01 15:00:35 -07:00
Andrew Waterman
996670a4a6 Point to correct Chisel commit 2015-10-01 10:31:29 -07:00
Howard Mao
a76f0bf8fb fix involuntary release bug in rocket ProbeUnit 2015-09-30 17:26:48 -07:00
Andrew Waterman
8da7be3211 More Chisel3 compatibility fixes 2015-09-30 14:37:40 -07:00
Andrew Waterman
0fe16ac1c0 Chisel3 compatibility fixes 2015-09-30 14:37:00 -07:00
Howard Mao
1e7f656527 get release block address from inner release 2015-09-28 15:02:51 -07:00
Andrew Waterman
79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Howard Mao
353b00c8a1 revert some Chisel3-related changes and fix tlb bugs 2015-09-26 22:08:06 -07:00
Howard Mao
c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Andrew Waterman
3b1da4c57e Revert "replace remaining uses of Vec.fill" 
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
 2015-09-25 17:06:57 -07:00
Andrew Waterman
20b7a82ab6 Use Vec.fill, not Vec.apply, when making Vec literals 2015-09-25 17:06:52 -07:00
Andrew Waterman
2179cb64ae Let isRead be true for store-conditional 
This works around a deadlock bug in the L1 D$, and is arguably true.
 2015-09-25 15:28:02 -07:00
Howard Mao
7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao
0e67d824b4 fix NASTI interconnect bug 2015-09-25 12:12:34 -07:00
Howard Mao
308022210a use updated NASTI channel constructors 2015-09-25 12:07:27 -07:00
Howard Mao
8c4ac0f4f3 make sure CSR/SCR data width matches xLen 2015-09-25 12:07:03 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Schuyler Eldridge
f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE 
Fixes #17
 2015-09-24 23:56:41 -04:00
Howard Mao
c20ed350a0 even more Chisel3 compatability changes 2015-09-24 17:55:41 -07:00
Howard Mao
d1f2d40a90 replace remaining uses of Vec.fill 2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118 ReorderQueue uses Vec of Bools instead of Bits for roq_free 2015-09-24 17:43:53 -07:00
Howard Mao
1c0111cc70 uncore merge commit 2015-09-24 17:10:45 -07:00
Howard Mao
83740dfaa5 Merge branch 'master' of github.com:ucb-bar/uncore 2015-09-24 17:10:09 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
4a85c5a510 pull in hardfloat fixes 2015-09-24 16:58:49 -07:00