cdc476a370
change Rocc parameterization
2015-12-01 17:56:09 -08:00
e0d849fec5
Fix zscale testing
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Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
5eeb8969f6
fix zscale build (run still fails)
2015-12-01 16:20:34 -08:00
c8c68e75bb
base NGenerators on NTiles, not the other way around
2015-12-01 15:26:09 -08:00
e4043570bd
bump groundtest and hardfloat
2015-11-30 18:06:15 -08:00
40d68406d6
use xlen parameter for ALU
2015-11-30 18:04:44 -08:00
ec4ade988b
[travis] add multiple configs including rocc
2015-11-28 07:17:49 -08:00
7259239ba4
Merge pull request #31 from ucb-bar/multirocc
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implement support for multiple RoCC accelerators
2015-11-28 08:56:07 -05:00
23f0756978
implement support for multiple RoCC accelerators
2015-11-26 12:49:04 -08:00
e25a020e60
Construct device tree ROM in MMIO region
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Rebuild riscv-tools for this to work!
2015-11-25 21:23:37 -08:00
e52685f2e9
Fix LoadGen zero flag
2015-11-25 20:52:30 -08:00
27df04354f
Add ROM with NASTI interface
2015-11-25 20:04:31 -08:00
49d93da87e
Factor out more common zscale code
2015-11-24 19:17:21 -08:00
52b25c3da0
Factor out more common zscale code
2015-11-24 18:34:03 -08:00
1761db3272
Factor out some common code from zscale
2015-11-24 18:14:06 -08:00
57e82442a1
Make LoadGen and StoreGen generic
2015-11-24 18:12:42 -08:00
ec6bfde9a3
fix WritebackUnit issue in uncore
2015-11-21 16:11:22 -08:00
ee6514e4f4
make sure WritebackUnit sends correct probe addresses
2015-11-21 15:55:11 -08:00
04383a31f5
Revert "make sure L2MetadataArray assigns unoccupied way if available"
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This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
2015-11-21 10:35:40 -08:00
9d50f37289
fix unused set issue for multiple L2 cache banks
2015-11-20 23:26:28 -08:00
3c95afebc6
Shift set index for multi-bank configurations
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Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
2015-11-20 23:24:57 -08:00
55a85cc67a
make sure wmask is passed for PutBlock in broadcast hub
2015-11-20 14:09:24 -08:00
941b64cd62
make partial write-masking PutBlock constructor always set alloc bit
2015-11-20 13:34:07 -08:00
ad3b7fd0e1
adjust CacheFillTest configuration
2015-11-19 10:52:14 -08:00
24f7b9f472
make sure L2MetadataArray assigns unoccupied way if available
2015-11-19 10:45:54 -08:00
4806f72b08
add CacheFillTest to check L2 conflict misses
2015-11-19 00:16:28 -08:00
3514b6eb87
add some more useful configurations
2015-11-18 22:11:17 -08:00
379d43d5f4
make MultiChannel routing more performant
2015-11-18 22:11:17 -08:00
ea8ba49805
improve memory system: specialize MultiChannel routing
2015-11-18 21:58:22 -08:00
e50c7ad306
add NASTI error assertions back in
2015-11-18 17:05:54 -08:00
2b977325e3
Make prefetch type available in a_type, issue probeInvalidates for putPrefetches
2015-11-16 23:26:13 -08:00
5195a5b891
Remove IPI network
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This is now provided via MMIO.
2015-11-16 21:53:14 -08:00
d426ecee78
Remove IPI network
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This is now provided via MMIO.
2015-11-16 21:52:24 -08:00
0290635454
amo_shift_bits -> amo_shift_bytes
2015-11-16 19:07:58 -08:00
485f1b7bd7
bump uncore
2015-11-16 18:14:03 -08:00
64aaf71b06
L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type.
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Transaction metadata for primary and seconday misses now stored in the secondary miss queue.
Added BuiltInAcquireBuilder factory.
2015-11-16 18:10:09 -08:00
03fa06e6e7
fix prefetch lockup on L2 hit
2015-11-15 12:51:34 -08:00
8916c7e99c
push rocket
2015-11-14 16:43:28 -08:00
6a6371fdb6
move to new version of hardfloat
2015-11-14 14:50:13 -08:00
e12efab423
skip meta_write state if no meta write pending
2015-11-13 13:50:35 -08:00
a1063bad54
fix issues with non-allocating put/get
2015-11-12 15:54:34 -08:00
7e7d688a01
make sure L2 passes no-alloc acquires through to outer memory
2015-11-12 15:40:58 -08:00
b3865c370a
make sure correct addr_beat is sent for Get response by narrower/converter
2015-11-12 15:40:38 -08:00
f397d61033
add alloc option to Put constructor
2015-11-12 11:39:59 -08:00
7733fbe6a3
make sure no-alloc write still updates data array if there is a cache hit
2015-11-12 11:39:36 -08:00
97d0e195ae
Merge pull request #28 from ucb-bar/yusnup
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Don't re-generate the .d files on "make clean"
2015-11-12 00:46:21 -08:00
07f0e6be94
Don't re-generate the .d files on "make clean"
2015-11-12 00:41:55 -08:00
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
