d0988902f2
fix NASTI -> HASTI bridge
2016-05-31 19:47:50 -07:00
8f269b2eec
stall for more cycles in Hasti test
2016-05-31 19:46:42 -07:00
1311e78d3f
Add blocking D$ flush support
2016-05-31 19:28:41 -07:00
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
6d82c0d156
Add M_FLUSH_ALL command
2016-05-31 19:25:31 -07:00
50e3caef36
get rid of Zscale file I missed last time
2016-05-31 14:33:38 -07:00
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
56897f707a
Don't rely on Mux1H output when no inputs are hot
2016-05-27 13:38:01 -07:00
3ee5144923
Fix TLB tag check logic when ASIDs are present
2016-05-27 12:24:17 -07:00
056d7ec93a
Drive hmastlock low in Nasti-Hasti converter
2016-05-27 12:23:18 -07:00
2a7e7172a9
Update docs for the trace generator
2016-05-27 10:54:35 +01:00
8afdd7e3da
Work around PutBlocks draining into data array prematurely
2016-05-26 23:08:05 -07:00
c104b57c52
Use BitPat implicit conversion in instruction decoder
2016-05-26 22:23:21 -07:00
96fa1eb6ad
Add UInt->BitPat implicit conversion
...
This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
2016-05-26 18:52:53 -07:00
10f0e13c25
Use more parsimonious queue depths
2016-05-26 18:04:22 -07:00
3cc236e9c4
By default, use same TileLink width everywhere
...
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
391a9b9110
Use buses, rather than crossbars, by default in TLInterconnect
...
We should eventually parameterize this, of course.
2016-05-26 16:10:42 -07:00
75f06d6e84
Use generic TileLink width adapter
2016-05-26 16:00:17 -07:00
b6d26e90f8
Add generic TileLink width adapter
2016-05-26 15:59:42 -07:00
e036d3a04a
Chisel3: gender issue
2016-05-26 15:59:08 -07:00
8139f71dfb
Work around Chisel2 bug
...
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
2016-05-26 12:37:31 -07:00
b734beec06
Update build instructions
...
The emulator now requires an ELF file even when running ground tests.
(The ELF contains the tohost and fromhost addresses for communication
with the FESVR.)
2016-05-26 14:42:26 +01:00
a2b9d337b6
No need for full-throughput queues in NastiErrorSlave
2016-05-26 01:03:40 -07:00
2ece3e6102
Use Mem for ReorderQueue data
...
This might improve FPGA QoR.
2016-05-26 01:02:56 -07:00
ddfa30e215
Work around zero-width wire limitations
2016-05-26 00:48:54 -07:00
0c50bfcfb3
Work around more zero-width wire cases
2016-05-25 21:47:48 -07:00
22568de5f3
Work around another zero-width wire limitation
2016-05-25 21:42:02 -07:00
e2755a0f0a
Work around zero-width wire limitation in HTIF
2016-05-25 20:39:53 -07:00
3e238adc67
rtc: fix acquire message type check
2016-05-25 20:37:48 -07:00
40f38dde63
Work around lack of zero-width wires in D$
2016-05-25 19:44:31 -07:00
976d4d3184
ahb: AHB parameters should match TileLink parameters by default
...
Closes #116
2016-05-25 18:01:25 -07:00
ec0d178010
Support M-mode-only implementations
2016-05-25 15:40:53 -07:00
00ea9a7d82
Remove most of mstatus when user mode isn't supported
2016-05-25 15:37:32 -07:00
5442b89664
Remove unnecessary muxes in RV32 MulDiv
2016-05-25 14:27:02 -07:00
9aa724706e
Don't include RV64 instructions in RV32 decode table
2016-05-25 14:26:45 -07:00
7f1792cba3
ahb: backport bridge to chisel2
...
Closes #47
2016-05-25 13:40:24 -07:00
da105a5944
Don't allow travis to recurse through submodules
2016-05-25 13:27:49 -07:00
1c8745dfd2
ahb: backport to chisel2
...
Merges #16
2016-05-25 12:11:26 -07:00
da566e7d6a
build: use local sbt when building firrtl
2016-05-25 11:48:03 -07:00
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
a8462d3cfc
bump chisel
2016-05-25 11:09:50 -07:00
213bb26367
Drive invalidate_lr signal
...
The DCache input for invalidating LR reservations was dangling. Now
we wire it to false.
2016-05-25 13:27:12 +01:00
a9599302bd
fix cloneType in nasti.scala ( #14 )
2016-05-24 17:10:17 -07:00
5bc78aba99
Merge pull request #15 from terpstra/ahb
...
Ahb
2016-05-24 17:06:03 -07:00
c49cb10c74
Merge pull request #42 from terpstra/ahb
...
Ahb
2016-05-24 17:02:15 -07:00
4605b616c1
Fix bug in D$ AMO/storegen logic
2016-05-24 16:26:07 -07:00
88cc91db75
Ignore way_en in MetadataArray for direct-mapped caches
2016-05-24 15:47:09 -07:00
5dac7b818d
Support set associativity in blocking D$
2016-05-24 15:45:52 -07:00
e0addb5723
Support uncached AMOs in blocking D$
2016-05-24 15:45:35 -07:00
f14d87e327
Support larger I$ sets when VM is disabled
2016-05-24 15:44:59 -07:00
Howard Mao
Andrew Waterman
Matthew Naylor
Wesley W. Terpstra
Donggyu
Andrew Waterman