b09832f1b5
ICache now returns the "next PC" signal.
...
useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
c746ef8702
fix bug in rocc port resp for FPtoInt instructions
2015-05-04 11:20:55 -07:00
8832b454ce
add plugins to make scala doc site and publish to ghpages
2015-04-29 15:34:56 -07:00
1e05fc0525
First pages commit
2015-04-29 13:18:26 -07:00
b9fb1bb46e
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-04-29 00:43:53 -07:00
3673295d03
network shim cleanup
2015-04-27 16:59:30 -07:00
09e30041ed
Voluntary Writeback tracker rewrite
2015-04-27 12:56:33 -07:00
a37fad2e9b
Merge branch 'retimeable-frontend' into rocc-fpu-port
2015-04-22 14:23:52 -07:00
1f410ac42c
move fetch buffer into frontend to allow retiming
2015-04-22 11:26:03 -07:00
11b5222d01
Refactored WritebackUnit
2015-04-21 22:23:04 -07:00
4c7969b2b3
Metadata docs and api cleanup
2015-04-20 16:32:09 -07:00
a315fe93c1
simplify ClientMetadata.makeRelease
2015-04-20 10:46:24 -07:00
f66a9fd7a6
simplify ClientMetadata.makeRelease
2015-04-20 10:46:02 -07:00
6d40a61060
TileLink scala doc and parameter renaming
2015-04-19 22:06:44 -07:00
ca5b3d988d
Merge branch 'master' into rocc-fpu-port
2015-04-19 15:00:00 -07:00
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
ba7a8b1752
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
2015-04-17 16:55:20 -07:00
73fa28521d
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
2015-04-16 15:22:08 -07:00
ce3271aef2
refactor LNClients and LNManagers
2015-04-15 15:48:36 -07:00
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
90f800d87d
Grant bugfixes and more comments
2015-04-13 15:57:06 -07:00
24bb032ede
Merge pull request #7 from ccelio/master
...
Rocket front-end can now fetch 4 instructions; added assert to dcache; refactoring
2015-04-12 19:18:23 -07:00
517d0d4b89
feedback on PR
2015-04-12 18:44:03 -07:00
4d6ebded02
Added assert to nbdcache
2015-04-11 02:58:34 -07:00
a564f08702
Rename dmem.sret signal to more accurate invalidate_lr
2015-04-11 02:26:33 -07:00
8fc2d38ca9
Removed unnecessary signal in CSRIO
2015-04-11 02:20:34 -07:00
2f88c5ca9d
Renamed PCR to CSR
2015-04-11 02:16:44 -07:00
11dbd4221a
Fixed front-end to support four-wide fetch.
2015-04-10 17:53:47 -07:00
bd72db92c1
update rocc port to use fdiv/sqrt
2015-04-07 15:02:02 -07:00
879a4a0bcd
Update Makefile
...
Change default shell to bash shell.
2015-04-06 15:05:43 -07:00
887a8de189
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
2015-04-06 13:48:44 -07:00
3cf1778c92
moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled
2015-04-06 12:22:23 -07:00
9708d25dff
Restructure L2 state machine and utilize HeaderlessTileLinkIO
2015-04-06 12:19:51 -07:00
9ade0e41cc
Integrate divide/sqrt unit
2015-04-04 16:39:17 -07:00
fe27b9b1b2
Support writing sstatus.fs even without an FPU
2015-04-04 15:20:18 -07:00
bce62d5774
Update PTE format to reflect reserved bits
2015-04-04 15:19:15 -07:00
a369d8f17f
Add fpu port to the rocc interface
2015-04-02 01:30:11 -07:00
ced627f00a
slight mod to pending_puts
...
cleaner state transition logic
2015-04-01 15:24:53 -07:00
c941f0a68e
New virtual memory implementation (Sv39)
2015-03-27 16:21:29 -07:00
d912ea265e
New virtual memory implementation (Sv39)
2015-03-27 16:20:59 -07:00
8959b2e81a
TileLinkEnqueuer
2015-03-26 13:29:52 -07:00
b7af610569
broadcast hub bugfix
2015-03-26 11:29:04 -07:00
4176edaa34
clean up tracker allocation
2015-03-26 10:17:51 -07:00
faada5f110
Mask off LSBs of sepc/mepc/stvec
...
Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.
2015-03-25 00:20:58 -07:00
543ac91cf2
Misaligned fetches can't happen at the I$ anymore
...
They are caught before the I$ ever sees them, so leverage that fact.
2015-03-24 23:55:43 -07:00
90b31586ff
Misc. CSR fixes/improvements
...
- Support RV32 mstatus register
- Don't ignore mstatus.stie bit
- Support custom M-mode R/W CSRs for Raven chip
2015-03-24 23:50:18 -07:00
822698b567
support disabling supervisor mode (via UseVM parameter)
2015-03-24 19:32:45 -07:00
0332c1e7fe
Reduce latency of page table walks
...
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
2015-03-24 18:58:38 -07:00
31d17cbf86
Hard-wire LSB of JALR to 0, as sent to BTB
2015-03-21 00:16:34 -07:00
