1
0

Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port

This commit is contained in:
Colin Schmidt 2015-04-16 15:22:08 -07:00
commit 73fa28521d
8 changed files with 33 additions and 27 deletions

View File

@ -21,7 +21,7 @@ trait ScalarOpConstants {
val PC_EX = UInt(0, 2)
val PC_MEM = UInt(1, 2)
val PC_WB = UInt(2, 2)
val PC_PCR = UInt(3, 2)
val PC_CSR = UInt(3, 2)
val A1_X = Bits("b??", 2)
val A1_ZERO = UInt(0, 2)

View File

@ -93,7 +93,6 @@ class CSRFileIO extends CoreBundle {
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth)))
val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen))
val cause = UInt(INPUT, xLen)
val mbadaddr_wen = Bool(INPUT)
val pc = SInt(INPUT, vaddrBits+1)
val fatc = Bool(OUTPUT)
val time = UInt(OUTPUT, xLen)

View File

@ -553,7 +553,7 @@ class Control extends CoreModule
take_pc_wb := replay_wb || wb_xcpt || io.dpath.eret
io.dpath.sel_pc :=
Mux(wb_xcpt || io.dpath.eret, PC_PCR, // exception or [m|s]ret
Mux(wb_xcpt || io.dpath.eret, PC_CSR, // exception or [m|s]ret
Mux(replay_wb, PC_WB, // replay
PC_MEM))
@ -589,7 +589,7 @@ class Control extends CoreModule
io.dpath.bypass_src(i) := PriorityEncoder(doBypass(i))
}
// stall for RAW/WAW hazards on PCRs, loads, AMOs, and mul/div in execute stage.
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
val id_renx1_not0 = id_ctrl.rxs1 && id_raddr1 != UInt(0)
val id_renx2_not0 = id_ctrl.rxs2 && id_raddr2 != UInt(0)
val id_wen_not0 = id_ctrl.wxd && id_waddr != UInt(0)
@ -605,7 +605,7 @@ class Control extends CoreModule
io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
// stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage.
// stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
val mem_mem_cmd_bh =
if (params(FastLoadWord)) Bool(!params(FastLoadByte)) && mem_reg_slow_bypass
else Bool(true)
@ -674,7 +674,7 @@ class Control extends CoreModule
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.typ := ex_ctrl.mem_type
io.dmem.req.bits.phys := Bool(false)
io.dmem.sret := wb_xcpt // obviously not an sret, but sufficient
io.dmem.invalidate_lr := wb_xcpt
io.rocc.cmd.valid := wb_rocc_val
io.rocc.exception := wb_xcpt && io.dpath.status.xs.orR

View File

@ -166,17 +166,17 @@ class Datapath extends CoreModule
require(params(CoreDCacheReqTagBits) >= 6)
// processor control regfile read
val pcr = Module(new CSRFile)
pcr.io.host <> io.host
pcr.io <> io.ctrl
pcr.io <> io.fpu
pcr.io.rocc <> io.rocc
pcr.io.pc := wb_reg_pc
pcr.io.uarch_counters.foreach(_ := Bool(false))
val csr = Module(new CSRFile)
csr.io.host <> io.host
csr.io <> io.ctrl
csr.io <> io.fpu
csr.io.rocc <> io.rocc
csr.io.pc := wb_reg_pc
csr.io.uarch_counters.foreach(_ := Bool(false))
io.ptw.ptbr := pcr.io.ptbr
io.ptw.invalidate := pcr.io.fatc
io.ptw.status := pcr.io.status
io.ptw.ptbr := csr.io.ptbr
io.ptw.invalidate := csr.io.fatc
io.ptw.status := csr.io.status
// memory stage
mem_reg_kill := ex_reg_kill
@ -246,7 +246,7 @@ class Datapath extends CoreModule
}
wb_wdata := Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data_subword,
Mux(io.ctrl.ll_wen, ll_wdata,
Mux(io.ctrl.csr_cmd != CSR.N, pcr.io.rw.rdata,
Mux(io.ctrl.csr_cmd != CSR.N, csr.io.rw.rdata,
wb_reg_wdata)))
val wb_wen = io.ctrl.ll_wen || io.ctrl.wb_wen
@ -258,9 +258,9 @@ class Datapath extends CoreModule
io.ctrl.fp_sboard_clra := dmem_resp_waddr
// processor control regfile write
pcr.io.rw.addr := wb_reg_inst(31,20)
pcr.io.rw.cmd := io.ctrl.csr_cmd
pcr.io.rw.wdata := wb_reg_wdata
csr.io.rw.addr := wb_reg_inst(31,20)
csr.io.rw.cmd := io.ctrl.csr_cmd
csr.io.rw.wdata := wb_reg_wdata
io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst)
io.rocc.cmd.bits.rs1 := wb_reg_wdata
@ -269,7 +269,7 @@ class Datapath extends CoreModule
// hook up I$
io.imem.req.bits.pc :=
Mux(io.ctrl.sel_pc === PC_MEM, mem_npc,
Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
Mux(io.ctrl.sel_pc === PC_CSR, csr.io.evec,
wb_reg_pc)).toUInt // PC_WB
io.imem.btb_update.bits.pc := mem_reg_pc
io.imem.btb_update.bits.target := io.imem.req.bits.pc
@ -283,7 +283,7 @@ class Datapath extends CoreModule
io.ctrl.wb_waddr := wb_reg_inst(11,7)
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.host.id, pcr.io.time(32,0), io.ctrl.retire, wb_reg_pc,
io.host.id, csr.io.time(32,0), io.ctrl.retire, wb_reg_pc,
Mux(wb_wen, wb_waddr, UInt(0)), wb_wdata, wb_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),

View File

@ -114,8 +114,11 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
io.cpu.resp.bits.pc := s2_pc
require(coreFetchWidth * coreInstBytes <= rowBytes)
val fetch_data =
if (coreFetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock
else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
val fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
for (i <- 0 until coreFetchWidth) {
io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
}

View File

@ -83,7 +83,7 @@ class HellaCacheIO extends CoreBundle {
val resp = Valid(new HellaCacheResp).flip
val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip
val xcpt = (new HellaCacheExceptions).asInput
val sret = Bool(OUTPUT)
val invalidate_lr = Bool(OUTPUT)
val ordered = Bool(INPUT)
}
@ -686,6 +686,10 @@ class HellaCache extends L1HellaCacheModule {
io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
assert (!(Reg(next=
(io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&
io.cpu.resp.valid), "DCache exception occurred - cache response not killed.")
// tags
def onReset = L1Metadata(UInt(0), ClientMetadata.onReset)
val meta = Module(new MetadataArray(onReset _))
@ -752,7 +756,7 @@ class HellaCache extends L1HellaCacheModule {
lrsc_count := 0
}
}
when (io.cpu.sret) { lrsc_count := 0 }
when (io.cpu.invalidate_lr) { lrsc_count := 0 }
val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
for (w <- 0 until nWays) {

View File

@ -125,7 +125,7 @@ class AccumulatorExample extends RoCC
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
io.mem.req.bits.data := Bits(0) // we're not performing any stores...
io.mem.sret := false
io.mem.invalidate_lr := false
io.imem.acquire.valid := false
io.imem.grant.ready := false

View File

@ -25,7 +25,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
val ptw = Module(new PTW(params(NPTWPorts)))
val core = Module(new Core, { case CoreName => "Rocket" })
dcache.io.cpu.sret := core.io.dmem.sret // Bypass sret to dcache
dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem