4c7c3f5bb2
add test generate for ZscaleTop
2015-07-14 16:26:28 -07:00
d6df479870
move 'include /Makefrag' out of top-level Makefrag
2015-07-14 16:13:32 -07:00
76046c52fe
Cleanup testing rv64uf
2015-07-13 18:58:58 -07:00
186e32a546
Merge pull request #9 from ucb-bar/param-based-makefrags
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Param-based makefrag generation
2015-07-13 15:51:28 -07:00
302cd3e638
Added BuildZscale param for use in Top and makefrag generation
2015-07-13 15:46:42 -07:00
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
a78e28523c
Chisel3: Don't mix Mux types
2015-07-11 14:06:08 -07:00
e76a9d3493
Chisel3: Don't mix Mux types
2015-07-11 14:05:39 -07:00
5dc3da008e
Use Chisel3 SeqMem construct
2015-07-11 13:36:26 -07:00
3233867390
Use Chisel3 SeqMem construct
2015-07-11 13:34:57 -07:00
4e4015089d
rename Configs source
2015-07-09 15:04:11 -07:00
3573fcdf2d
bump uncore
2015-07-09 14:42:38 -07:00
fb91e3e1ab
minor metadata API update (0.3.3)
2015-07-09 14:36:09 -07:00
80ad1eac70
Update README.md
2015-07-08 19:05:18 -07:00
09e29e8fe0
add zscale
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only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
e6a13cdeba
New machine-mode timer facility
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Mirroring Andrew's commit to reference-chip
2015-07-07 17:26:07 -07:00
4fbb0f80ff
Added some multicore/multibanks named ChiselConfigs
2015-07-06 18:21:06 -07:00
854fd64fba
Added optional Makefile includes for private chip repos
2015-07-06 17:15:27 -07:00
5ed2899e56
Merge pull request #10 from wsong83/fix
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L1 D$ writeback unit, reduce re-read data array
2015-07-06 15:18:49 -07:00
5362e2bbbd
New machine-mode timer facility
2015-07-05 16:38:49 -07:00
55059632c4
Temporarily use HTIF to push RTC value to cores
2015-07-05 16:19:39 -07:00
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
d7cb60e8fa
L2 WritebackUnit bug fix
2015-07-02 13:52:40 -07:00
12d8d8c5e3
Merge pull request #8 from seldridge/master
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Fix FPGA/VLSI Mem Gen for Python 2 and 3 Environments
2015-06-28 08:54:24 -05:00
b4cd8c5981
Fix vlsi_mem_gen for Python 2 or 3
2015-06-25 12:48:31 -07:00
a42832fc70
Fix fpga_mem_gen for Python 2 and 3 Environments
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Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
2015-06-25 11:03:33 -07:00
b4e38192a1
Fix (?) L2$ miss bug
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The victim's metadata was incorrectly used for the new line.
2015-06-24 18:01:56 -07:00
5e009ecc75
Fix an apparently benign PC sign-extension bug
2015-06-11 16:08:39 -07:00
ea76800d1a
Fix data array reset bug
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io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.
This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon. It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
2015-06-11 15:28:23 -07:00
4b6cd7f3eb
Merge branch 'master' of ucb-bar/rocket into rocc-fpu-port for priv1.7
2015-06-03 15:51:53 -07:00
4db60d9e9d
code clean in dcache, no need to check the condition twice.
2015-06-02 22:06:12 +01:00
b6e68773fd
nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array.
2015-05-30 16:25:27 +01:00
f3a838cedf
nasti converters, hub bugfix
2015-05-21 19:49:17 -07:00
a59ba39310
bump submodule for fpga-zynq
2015-05-21 11:26:57 -07:00
38edbc78e5
Merge pull request #5 from amsharifian/master
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Update Makefile
2015-05-21 11:24:25 -07:00
6a9390c50e
Avoid spurious D$ assertion failures
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For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
2015-05-19 03:00:53 -07:00
f460cb6c54
Update to privileged architecture 1.7
2015-05-19 02:32:21 -07:00
254498042a
Fix Split for 0-width wires
2015-05-18 18:23:17 -07:00
d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
c202449e34
first version NASTI IOs
2015-05-14 15:29:49 -07:00
90c9ee7b04
fix unalloc putblocks
2015-05-14 12:37:35 -07:00
a7fa77c7fc
track operand size for Gets
2015-05-13 23:28:18 -07:00
172c372d3e
L2 alloc cleanup
2015-05-12 17:14:06 -07:00
5fdae2cb61
Merge branch 'master' of github.com:ucb-bar/uncore
2015-05-07 16:18:23 -07:00
fc883b5049
rm index.html
2015-05-07 16:17:40 -07:00
8362eba00f
Merge branch 'gh-pages'
2015-05-07 16:16:13 -07:00
aec24cf1a7
readme
2015-05-07 16:16:07 -07:00
62b6f24798
Delete TileLink0.3.1Specification.pdf
2015-05-07 15:43:06 -07:00
90ced93eeb
Merge branch 'master' into gh-pages
2015-05-07 12:35:14 -07:00
4cef8c9cd4
Added MemIOArbiter
2015-05-07 10:55:38 -07:00
