Merge branch 'master' into rocc-fpu-port
This commit is contained in:
Albert Ou
commit
ca5b3d988d
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@ -52,27 +52,3 @@ class HellaCacheArbiter(n: Int) extends Module
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io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
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}
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}
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class RocketUncachedTileLinkIOArbiter(n: Int) extends TileLinkArbiterLike(n)
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with AppendsArbiterId {
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val io = new Bundle {
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val in = Vec.fill(n){new HeaderlessUncachedTileLinkIO}.flip
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val out = new HeaderlessUncachedTileLinkIO
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}
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hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
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hookupFinish(io.in.map(_.finish), io.out.finish)
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hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
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}
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class RocketTileLinkIOArbiter(n: Int) extends TileLinkArbiterLike(n)
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with AppendsArbiterId {
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val io = new Bundle {
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val in = Vec.fill(n){new HeaderlessTileLinkIO}.flip
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val out = new HeaderlessTileLinkIO
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}
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hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
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hookupClientSourceHeaderless(io.in.map(_.release), io.out.release)
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hookupFinish(io.in.map(_.finish), io.out.finish)
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hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
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hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
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}
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@ -1,148 +0,0 @@
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// See LICENSE for license details.
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package rocket
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import Chisel._
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import uncore._
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import Util._
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abstract class Decoding
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{
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def uncorrected: Bits
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def corrected: Bits
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def correctable: Bool
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def uncorrectable: Bool
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def error = correctable || uncorrectable
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}
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abstract class Code
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{
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def width(w0: Int): Int
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def encode(x: Bits): Bits
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def decode(x: Bits): Decoding
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}
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class IdentityCode extends Code
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{
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def width(w0: Int) = w0
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def encode(x: Bits) = x
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def decode(y: Bits) = new Decoding {
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def uncorrected = y
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def corrected = y
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def correctable = Bool(false)
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def uncorrectable = Bool(false)
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}
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}
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class ParityCode extends Code
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{
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def width(w0: Int) = w0+1
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def encode(x: Bits) = Cat(x.xorR, x)
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def decode(y: Bits) = new Decoding {
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def uncorrected = y(y.getWidth-2,0)
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def corrected = uncorrected
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def correctable = Bool(false)
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def uncorrectable = y.xorR
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}
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}
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class SECCode extends Code
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{
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def width(k: Int) = {
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val m = k.log2 + 1
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k + m + ((1 << m) < m+k+1).toInt
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}
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def encode(x: Bits) = {
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val k = x.getWidth
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require(k > 0)
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val n = width(k)
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val y = for (i <- 1 to n) yield {
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if (isPow2(i)) {
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val r = for (j <- 1 to n; if j != i && (j & i) != 0)
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yield x(mapping(j))
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r reduce (_^_)
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} else
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x(mapping(i))
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}
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Vec(y).toBits
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}
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def decode(y: Bits) = new Decoding {
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val n = y.getWidth
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require(n > 0 && !isPow2(n))
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val p2 = for (i <- 0 until log2Up(n)) yield 1 << i
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val syndrome = p2 map { i =>
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val r = for (j <- 1 to n; if (j & i) != 0)
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yield y(j-1)
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r reduce (_^_)
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}
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val s = Vec(syndrome).toBits
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private def swizzle(z: Bits) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits
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def uncorrected = swizzle(y)
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def corrected = swizzle(((y.toUInt << 1) ^ UIntToOH(s)) >> 1)
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def correctable = s.orR
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def uncorrectable = Bool(false)
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}
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private def mapping(i: Int) = i-1-log2Up(i)
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}
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class SECDEDCode extends Code
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{
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private val sec = new SECCode
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private val par = new ParityCode
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def width(k: Int) = sec.width(k)+1
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def encode(x: Bits) = par.encode(sec.encode(x))
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def decode(x: Bits) = new Decoding {
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val secdec = sec.decode(x(x.getWidth-2,0))
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val pardec = par.decode(x)
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def uncorrected = secdec.uncorrected
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def corrected = secdec.corrected
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def correctable = pardec.uncorrectable
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def uncorrectable = !pardec.uncorrectable && secdec.correctable
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}
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}
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object ErrGen
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{
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// generate a 1-bit error with approximate probability 2^-f
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def apply(width: Int, f: Int): Bits = {
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require(width > 0 && f >= 0 && log2Up(width) + f <= 16)
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UIntToOH(LFSR16()(log2Up(width)+f-1,0))(width-1,0)
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}
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def apply(x: Bits, f: Int): Bits = x ^ apply(x.getWidth, f)
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}
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class SECDEDTest extends Module
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{
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val code = new SECDEDCode
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val k = 4
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val n = code.width(k)
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val io = new Bundle {
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val original = Bits(OUTPUT, k)
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val encoded = Bits(OUTPUT, n)
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val injected = Bits(OUTPUT, n)
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val uncorrected = Bits(OUTPUT, k)
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val corrected = Bits(OUTPUT, k)
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val correctable = Bool(OUTPUT)
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val uncorrectable = Bool(OUTPUT)
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}
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val c = Counter(Bool(true), 1 << k)
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val numErrors = Counter(c._2, 3)._1
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val e = code.encode(c._1)
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val i = e ^ Mux(numErrors < 1, 0, ErrGen(n, 1)) ^ Mux(numErrors < 2, 0, ErrGen(n, 1))
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val d = code.decode(i)
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io.original := c._1
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io.encoded := e
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io.injected := i
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io.uncorrected := d.uncorrected
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io.corrected := d.corrected
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io.correctable := d.correctable
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io.uncorrectable := d.uncorrectable
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}
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@ -4,12 +4,9 @@ import Chisel._
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import uncore._
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import Util._
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case object ECCCode extends Field[Option[Code]]
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abstract trait L1CacheParameters extends CacheParameters with CoreParameters {
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val outerDataBeats = params(TLDataBeats)
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val outerDataBits = params(TLDataBits)
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val code = params(ECCCode).getOrElse(new IdentityCode)
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val refillCyclesPerBeat = outerDataBits/rowBits
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val refillCycles = refillCyclesPerBeat*outerDataBeats
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}
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@ -44,7 +41,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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val io = new Bundle {
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val cpu = new CPUFrontendIO().flip
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val ptw = new TLBPTWIO()
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val mem = new HeaderlessUncachedTileLinkIO
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val mem = new ClientUncachedTileLinkIO
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}
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val btb = Module(new BTB(btb_updates_out_of_order))
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@ -149,7 +146,7 @@ class ICache extends FrontendModule
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val req = Valid(new ICacheReq).flip
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val resp = Decoupled(new ICacheResp)
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val invalidate = Bool(INPUT)
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val mem = new HeaderlessUncachedTileLinkIO
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val mem = new ClientUncachedTileLinkIO
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}
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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@ -190,15 +187,10 @@ class ICache extends FrontendModule
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val s2_miss = s2_valid && !s2_any_tag_hit
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rdy := state === s_ready && !s2_miss
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val ser = Module(new FlowThroughSerializer(
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io.mem.grant.bits,
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refillCyclesPerBeat))
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ser.io.in <> io.mem.grant
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val (refill_cnt, refill_wrap) = Counter(ser.io.out.fire(), refillCycles) //TODO Zero width wire
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val narrow_grant = FlowThroughSerializer(io.mem.grant, refillCyclesPerBeat)
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val (refill_cnt, refill_wrap) = Counter(narrow_grant.fire(), refillCycles) //TODO Zero width wire
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val refill_done = state === s_refill && refill_wrap
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val refill_valid = ser.io.out.valid
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val refill_bits = ser.io.out.bits
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ser.io.out.ready := Bool(true)
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narrow_grant.ready := Bool(true)
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val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0)
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val entagbits = code.width(tagBits)
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@ -250,9 +242,9 @@ class ICache extends FrontendModule
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for (i <- 0 until nWays) {
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val data_array = Mem(Bits(width = code.width(rowBits)), nSets*refillCycles, seqRead = true)
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val s1_raddr = Reg(UInt())
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when (refill_valid && repl_way === UInt(i)) {
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val e_d = code.encode(refill_bits.payload.data)
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if(refillCycles > 1) data_array(Cat(s2_idx, refill_bits.payload.addr_beat)) := e_d
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when (narrow_grant.valid && repl_way === UInt(i)) {
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val e_d = code.encode(narrow_grant.bits.data)
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if(refillCycles > 1) data_array(Cat(s2_idx, refill_cnt)) := e_d
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else data_array(s2_idx) := e_d
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}
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// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
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@ -266,16 +258,10 @@ class ICache extends FrontendModule
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ack_q.io.enq.valid := refill_done && refill_bits.payload.requiresAck()
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ack_q.io.enq.bits.payload := refill_bits.payload.makeFinish()
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ack_q.io.enq.bits.header.dst := refill_bits.header.src
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// output signals
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io.resp.valid := s2_hit
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io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
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io.mem.acquire.valid := (state === s_request)
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io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
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io.mem.finish <> ack_q.io.deq
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// control state machine
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switch (state) {
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@ -284,7 +270,7 @@ class ICache extends FrontendModule
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invalidated := Bool(false)
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}
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is (s_request) {
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when (io.mem.acquire.ready && ack_q.io.enq.ready) { state := s_refill_wait }
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when (io.mem.acquire.ready) { state := s_refill_wait }
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}
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is (s_refill_wait) {
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when (io.mem.grant.valid) { state := s_refill }
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@ -97,6 +97,8 @@ class L1DataWriteReq extends L1DataReadReq {
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val data = Bits(width = encRowBits)
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}
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class L1RefillReq extends L1DataReadReq
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class L1MetaReadReq extends MetaReadReq {
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val tag = Bits(width = tagBits)
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}
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@ -140,12 +142,11 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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val tag = Bits(OUTPUT, tagBits)
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val mem_req = Decoupled(new Acquire)
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val mem_resp = new L1DataWriteReq().asOutput
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val refill = new L1RefillReq().asOutput // Data is bypassed
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new L1MetaWriteReq)
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val replay = Decoupled(new ReplayInternal)
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val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
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val mem_finish = Decoupled(new LogicalNetworkIO(new Finish))
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val mem_grant = Valid(new Grant).flip
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val wb_req = Decoupled(new WritebackReq)
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val probe_rdy = Bool(OUTPUT)
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}
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@ -168,11 +169,9 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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(states_before_refill.contains(state) ||
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(Vec(s_refill_req, s_refill_resp).contains(state) &&
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!cmd_requires_second_acquire))
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val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UInt(id)
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val gnt_multi_data = io.mem_grant.bits.payload.hasMultibeatData()
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val (refill_cnt, refill_count_done) = Counter(reply && gnt_multi_data, refillCycles) // TODO: Zero width?
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val refill_done = reply && (!gnt_multi_data || refill_count_done)
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val wb_done = reply && (state === s_wb_resp)
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val gnt_multi_data = io.mem_grant.bits.hasMultibeatData()
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val (refill_cnt, refill_count_done) = Counter(io.mem_grant.valid && gnt_multi_data, refillCycles) // TODO: Zero width?
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val refill_done = io.mem_grant.valid && (!gnt_multi_data || refill_count_done)
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val rpq = Module(new Queue(new ReplayInternal, params(ReplayQueueDepth)))
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd)
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@ -180,7 +179,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid
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val coh_on_grant = req.old_meta.coh.onGrant(
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incoming = io.mem_grant.bits.payload,
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incoming = io.mem_grant.bits,
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pending = req.cmd)
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val coh_on_hit = io.req_bits.old_meta.coh.onHit(io.req_bits.cmd)
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@ -195,7 +194,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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state := s_meta_write_resp
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}
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when (state === s_refill_resp) {
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when (reply) { new_coh_state := coh_on_grant }
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when (io.mem_grant.valid) { new_coh_state := coh_on_grant }
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when (refill_done) { state := s_meta_write_req }
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}
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when (io.mem_req.fire()) { // s_refill_req
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@ -204,7 +203,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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when (state === s_meta_clear && io.meta_write.ready) {
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state := s_refill_req
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}
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when (state === s_wb_resp && reply) {
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when (state === s_wb_resp && io.mem_grant.valid) {
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state := s_meta_clear
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}
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when (io.wb_req.fire()) { // s_wb_req
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@ -233,18 +232,9 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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}
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}
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val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ackq.io.enq.valid := (wb_done || refill_done) && io.mem_grant.bits.payload.requiresAck()
|
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ackq.io.enq.bits.payload := io.mem_grant.bits.payload.makeFinish()
|
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ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
|
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val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
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io.mem_finish.valid := ackq.io.deq.valid && can_finish
|
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ackq.io.deq.ready := io.mem_finish.ready && can_finish
|
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io.mem_finish.bits := ackq.io.deq.bits
|
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|
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io.idx_match := (state != s_invalid) && idx_match
|
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io.mem_resp := req
|
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io.mem_resp.addr := (if(refillCycles > 1) Cat(req_idx, refill_cnt) else req_idx) << rowOffBits
|
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io.refill.way_en := req.way_en
|
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io.refill.addr := (if(refillCycles > 1) Cat(req_idx, refill_cnt) else req_idx) << rowOffBits
|
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io.tag := req.addr >> untagBits
|
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io.req_pri_rdy := state === s_invalid
|
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io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
|
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|
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@ -262,18 +252,17 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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io.meta_write.bits.data.tag := io.tag
|
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io.meta_write.bits.way_en := req.way_en
|
||||
|
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io.wb_req.valid := state === s_wb_req && ackq.io.enq.ready
|
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io.wb_req.valid := state === s_wb_req
|
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io.wb_req.bits := req.old_meta.coh.makeVoluntaryWriteback(
|
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client_xact_id = UInt(id),
|
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addr_block = Cat(req.old_meta.tag, req_idx))
|
||||
io.wb_req.bits.way_en := req.way_en
|
||||
|
||||
io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready
|
||||
io.mem_req.valid := state === s_refill_req
|
||||
io.mem_req.bits := req.old_meta.coh.makeAcquire(
|
||||
addr_block = Cat(io.tag, req_idx).toUInt,
|
||||
client_xact_id = Bits(id),
|
||||
op_code = req.cmd)
|
||||
io.mem_finish <> ackq.io.deq
|
||||
|
||||
io.meta_read.valid := state === s_drain_rpq
|
||||
io.meta_read.bits.idx := req_idx
|
||||
|
|
@ -295,13 +284,12 @@ class MSHRFile extends L1HellaCacheModule {
|
|||
val req = Decoupled(new MSHRReq).flip
|
||||
val secondary_miss = Bool(OUTPUT)
|
||||
|
||||
val mem_req = Decoupled(new Acquire) //TODO make sure TLParameters are correct ?????
|
||||
val mem_resp = new L1DataWriteReq().asOutput
|
||||
val mem_req = Decoupled(new Acquire)
|
||||
val refill = new L1RefillReq().asOutput
|
||||
val meta_read = Decoupled(new L1MetaReadReq)
|
||||
val meta_write = Decoupled(new L1MetaWriteReq)
|
||||
val replay = Decoupled(new Replay)
|
||||
val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
|
||||
val mem_finish = Decoupled(new LogicalNetworkIO(new Finish))
|
||||
val mem_grant = Valid(new Grant).flip
|
||||
val wb_req = Decoupled(new WritebackReq)
|
||||
|
||||
val probe_rdy = Bool(OUTPUT)
|
||||
|
|
@ -320,7 +308,7 @@ class MSHRFile extends L1HellaCacheModule {
|
|||
val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
|
||||
|
||||
val wbTagList = Vec.fill(nMSHRs){Bits()}
|
||||
val memRespMux = Vec.fill(nMSHRs){new L1DataWriteReq}
|
||||
val refillMux = Vec.fill(nMSHRs){new L1RefillReq}
|
||||
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
|
||||
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
|
||||
val mem_req_arb = Module(new LockingArbiter(
|
||||
|
|
@ -328,7 +316,6 @@ class MSHRFile extends L1HellaCacheModule {
|
|||
nMSHRs,
|
||||
outerDataBeats,
|
||||
(a: Acquire) => a.hasMultibeatData()))
|
||||
val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), nMSHRs))
|
||||
val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
|
||||
val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs))
|
||||
val alloc_arb = Module(new Arbiter(Bool(), nMSHRs))
|
||||
|
|
@ -357,12 +344,13 @@ class MSHRFile extends L1HellaCacheModule {
|
|||
mshr.io.meta_read <> meta_read_arb.io.in(i)
|
||||
mshr.io.meta_write <> meta_write_arb.io.in(i)
|
||||
mshr.io.mem_req <> mem_req_arb.io.in(i)
|
||||
mshr.io.mem_finish <> mem_finish_arb.io.in(i)
|
||||
mshr.io.wb_req <> wb_req_arb.io.in(i)
|
||||
mshr.io.replay <> replay_arb.io.in(i)
|
||||
|
||||
mshr.io.mem_grant <> io.mem_grant
|
||||
memRespMux(i) := mshr.io.mem_resp
|
||||
mshr.io.mem_grant.valid := io.mem_grant.valid &&
|
||||
io.mem_grant.bits.client_xact_id === UInt(i)
|
||||
mshr.io.mem_grant.bits := io.mem_grant.bits
|
||||
refillMux(i) := mshr.io.refill
|
||||
|
||||
pri_rdy = pri_rdy || mshr.io.req_pri_rdy
|
||||
sec_rdy = sec_rdy || mshr.io.req_sec_rdy
|
||||
|
|
@ -377,12 +365,11 @@ class MSHRFile extends L1HellaCacheModule {
|
|||
meta_read_arb.io.out <> io.meta_read
|
||||
meta_write_arb.io.out <> io.meta_write
|
||||
mem_req_arb.io.out <> io.mem_req
|
||||
mem_finish_arb.io.out <> io.mem_finish
|
||||
wb_req_arb.io.out <> io.wb_req
|
||||
|
||||
io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
|
||||
io.secondary_miss := idx_match
|
||||
io.mem_resp := memRespMux(io.mem_grant.bits.payload.client_xact_id)
|
||||
io.refill := refillMux(io.mem_grant.bits.client_xact_id)
|
||||
|
||||
val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd)
|
||||
io.replay.bits.data := sdq(RegEnable(replay_arb.io.out.bits.sdq_id, free_sdq))
|
||||
|
|
@ -597,7 +584,7 @@ class HellaCache extends L1HellaCacheModule {
|
|||
val io = new Bundle {
|
||||
val cpu = (new HellaCacheIO).flip
|
||||
val ptw = new TLBPTWIO()
|
||||
val mem = new HeaderlessTileLinkIO
|
||||
val mem = new ClientTileLinkIO
|
||||
}
|
||||
|
||||
require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
|
||||
|
|
@ -806,7 +793,6 @@ class HellaCache extends L1HellaCacheModule {
|
|||
mshrs.io.req.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
|
||||
mshrs.io.req.bits.data := s2_req.data
|
||||
when (mshrs.io.req.fire()) { replacer.miss }
|
||||
|
||||
io.mem.acquire <> mshrs.io.mem_req
|
||||
|
||||
// replays
|
||||
|
|
@ -822,10 +808,9 @@ class HellaCache extends L1HellaCacheModule {
|
|||
val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
|
||||
releaseArb.io.out <> io.mem.release
|
||||
|
||||
val probe = DecoupledLogicalNetworkIOUnwrapper(io.mem.probe)
|
||||
prober.io.req.valid := probe.valid && !lrsc_valid
|
||||
probe.ready := prober.io.req.ready && !lrsc_valid
|
||||
prober.io.req.bits := probe.bits
|
||||
prober.io.req.valid := io.mem.probe.valid && !lrsc_valid
|
||||
io.mem.probe.ready := prober.io.req.ready && !lrsc_valid
|
||||
prober.io.req.bits := io.mem.probe.bits
|
||||
prober.io.rep <> releaseArb.io.in(1)
|
||||
prober.io.way_en := s2_tag_match_way
|
||||
prober.io.block_state := s2_hit_state
|
||||
|
|
@ -834,19 +819,16 @@ class HellaCache extends L1HellaCacheModule {
|
|||
prober.io.mshr_rdy := mshrs.io.probe_rdy
|
||||
|
||||
// refills
|
||||
val ser = Module(new FlowThroughSerializer(
|
||||
io.mem.grant.bits,
|
||||
refillCyclesPerBeat))
|
||||
ser.io.in <> io.mem.grant
|
||||
val refill = ser.io.out
|
||||
mshrs.io.mem_grant.valid := refill.fire()
|
||||
mshrs.io.mem_grant.bits := refill.bits
|
||||
refill.ready := writeArb.io.in(1).ready || !refill.bits.payload.hasData()
|
||||
writeArb.io.in(1).valid := refill.valid && refill.bits.payload.hasData()
|
||||
writeArb.io.in(1).bits := mshrs.io.mem_resp
|
||||
val narrow_grant = FlowThroughSerializer(io.mem.grant, refillCyclesPerBeat)
|
||||
mshrs.io.mem_grant.valid := narrow_grant.fire()
|
||||
mshrs.io.mem_grant.bits := narrow_grant.bits
|
||||
narrow_grant.ready := writeArb.io.in(1).ready || !narrow_grant.bits.hasData()
|
||||
writeArb.io.in(1).valid := narrow_grant.valid && narrow_grant.bits.hasData()
|
||||
writeArb.io.in(1).bits.addr := mshrs.io.refill.addr
|
||||
writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en
|
||||
writeArb.io.in(1).bits.wmask := SInt(-1)
|
||||
writeArb.io.in(1).bits.data := refill.bits.payload.data(encRowBits-1,0)
|
||||
readArb.io.out.ready := !refill.valid || refill.ready // insert bubble if refill gets blocked
|
||||
writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0)
|
||||
readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked
|
||||
readArb.io.out <> data.io.read
|
||||
|
||||
// writebacks
|
||||
|
|
@ -920,8 +902,6 @@ class HellaCache extends L1HellaCacheModule {
|
|||
|
||||
io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
|
||||
io.cpu.replay_next.bits := s1_req.tag
|
||||
|
||||
io.mem.finish <> mshrs.io.mem_finish
|
||||
}
|
||||
|
||||
// exposes a sane decoupled request interface
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ import Node._
|
|||
import uncore._
|
||||
import Util._
|
||||
|
||||
case object RoCCMemTagBits extends Field[Int]
|
||||
case object RoCCMaxTaggedMemXacts extends Field[Int]
|
||||
|
||||
class RoCCInstruction extends Bundle
|
||||
{
|
||||
|
|
@ -44,8 +44,8 @@ class RoCCInterface extends Bundle
|
|||
val interrupt = Bool(OUTPUT)
|
||||
|
||||
// These should be handled differently, eventually
|
||||
val imem = new HeaderlessUncachedTileLinkIO
|
||||
val dmem = new HeaderlessUncachedTileLinkIO
|
||||
val imem = new ClientUncachedTileLinkIO
|
||||
val dmem = new ClientUncachedTileLinkIO
|
||||
val iptw = new TLBPTWIO
|
||||
val dptw = new TLBPTWIO
|
||||
val pptw = new TLBPTWIO
|
||||
|
|
@ -129,10 +129,8 @@ class AccumulatorExample extends RoCC
|
|||
|
||||
io.imem.acquire.valid := false
|
||||
io.imem.grant.ready := false
|
||||
io.imem.finish.valid := false
|
||||
io.dmem.acquire.valid := false
|
||||
io.dmem.grant.ready := false
|
||||
io.dmem.finish.valid := false
|
||||
io.iptw.req.valid := false
|
||||
io.dptw.req.valid := false
|
||||
io.pptw.req.valid := false
|
||||
|
|
|
|||
|
|
@ -13,8 +13,8 @@ case object BuildRoCC extends Field[Option[() => RoCC]]
|
|||
|
||||
abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
|
||||
val io = new Bundle {
|
||||
val cached = new HeaderlessTileLinkIO
|
||||
val uncached = new HeaderlessUncachedTileLinkIO
|
||||
val cached = new ClientTileLinkIO
|
||||
val uncached = new ClientUncachedTileLinkIO
|
||||
val host = new HTIFIO
|
||||
}
|
||||
}
|
||||
|
|
@ -44,7 +44,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
|
|||
// otherwise, just hookup the icache
|
||||
io.uncached <> params(BuildRoCC).map { buildItHere =>
|
||||
val rocc = buildItHere()
|
||||
val memArb = Module(new RocketUncachedTileLinkIOArbiter(3))
|
||||
val memArb = Module(new ClientTileLinkIOArbiter(3))
|
||||
val dcIF = Module(new SimpleHellaCacheIF)
|
||||
core.io.rocc <> rocc.io
|
||||
dcIF.io.requestor <> rocc.io.mem
|
||||
|
|
|
|||
|
|
@ -6,14 +6,6 @@ import Chisel._
|
|||
import uncore._
|
||||
import scala.math._
|
||||
|
||||
class Unsigned(x: Int) {
|
||||
require(x >= 0)
|
||||
def clog2: Int = { require(x > 0); ceil(log(x)/log(2)).toInt }
|
||||
def log2: Int = { require(x > 0); floor(log(x)/log(2)).toInt }
|
||||
def isPow2: Boolean = x > 0 && (x & (x-1)) == 0
|
||||
def nextPow2: Int = if (x == 0) 1 else 1 << clog2
|
||||
}
|
||||
|
||||
object Util {
|
||||
implicit def intToUInt(x: Int): UInt = UInt(x)
|
||||
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user