Merge branch 'retimeable-frontend' into rocc-fpu-port
This commit is contained in:
commit
a37fad2e9b
@ -56,13 +56,14 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
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val s2_xcpt_if = Reg(init=Bool(false))
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val icbuf = Module(new Queue(new ICacheResp, 1, pipe=true))
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val msb = vaddrBits-1
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val lsb = log2Up(coreFetchWidth*coreInstBytes)
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val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
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val ntpc_0 = s1_pc + UInt(coreInstBytes*coreFetchWidth)
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val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
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val icmiss = s2_valid && !icache.io.resp.valid
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val icmiss = s2_valid && !icbuf.io.deq.valid
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val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
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val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
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val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
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@ -106,15 +107,17 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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icache.io.invalidate := io.cpu.invalidate
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icache.io.req.bits.ppn := tlb.io.resp.ppn
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icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icbuf.io.deq.valid)
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io.cpu.resp.bits.pc := s2_pc
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icbuf.io.enq <> icache.io.resp
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icbuf.io.deq.ready := !stall && !s1_same_block
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require(coreFetchWidth * coreInstBytes <= rowBytes)
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val fetch_data =
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if (coreFetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock
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else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
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if (coreFetchWidth * coreInstBytes == rowBytes) icbuf.io.deq.bits.datablock
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else icbuf.io.deq.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
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for (i <- 0 until coreFetchWidth) {
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io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
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@ -136,7 +139,6 @@ class ICacheReq extends FrontendBundle {
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}
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class ICacheResp extends FrontendBundle {
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val data = Bits(width = coreInstBits)
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val datablock = Bits(width = rowBits)
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}
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@ -158,9 +160,8 @@ class ICache extends FrontendModule
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val stall = !io.resp.ready
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val rdy = Bool()
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val s2_valid = Reg(init=Bool(false))
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val s2_addr = Reg(UInt(width = paddrBits))
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val s2_any_tag_hit = Bool()
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val refill_addr = Reg(UInt(width = paddrBits))
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val s1_any_tag_hit = Bool()
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val s1_valid = Reg(init=Bool(false))
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val s1_pgoff = Reg(UInt(width = pgIdxBits))
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@ -175,31 +176,31 @@ class ICache extends FrontendModule
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s1_pgoff := io.req.bits.idx
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}
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s2_valid := s1_valid && rdy && !io.req.bits.kill || io.resp.valid && stall
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when (s1_valid && rdy && !stall) {
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s2_addr := s1_addr
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}
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val out_valid = s1_valid && !io.req.bits.kill && state === s_ready
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val s1_idx = s1_addr(untagBits-1,blockOffBits)
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val s1_offset = s1_addr(blockOffBits-1,0)
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val s1_hit = out_valid && s1_any_tag_hit
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val s1_miss = out_valid && !s1_any_tag_hit
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rdy := state === s_ready && !s1_miss
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val s2_tag = s2_addr(tagBits+untagBits-1,untagBits)
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val s2_idx = s2_addr(untagBits-1,blockOffBits)
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val s2_offset = s2_addr(blockOffBits-1,0)
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val s2_hit = s2_valid && s2_any_tag_hit
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val s2_miss = s2_valid && !s2_any_tag_hit
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rdy := state === s_ready && !s2_miss
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when (s1_valid && state === s_ready && s1_miss) {
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refill_addr := s1_addr
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}
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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val narrow_grant = FlowThroughSerializer(io.mem.grant, refillCyclesPerBeat)
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val (refill_cnt, refill_wrap) = Counter(narrow_grant.fire(), refillCycles) //TODO Zero width wire
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val refill_done = state === s_refill && refill_wrap
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narrow_grant.ready := Bool(true)
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val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0)
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val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
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val entagbits = code.width(tagBits)
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val tag_array = Mem(Bits(width = entagbits*nWays), nSets, seqRead = true)
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val tag_raddr = Reg(UInt())
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when (refill_done) {
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val wmask = FillInterleaved(entagbits, if (isDM) Bits(1) else UIntToOH(repl_way))
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val tag = code.encode(s2_tag).toUInt
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tag_array.write(s2_idx, Fill(nWays, tag), wmask)
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val tag = code.encode(refill_tag).toUInt
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tag_array.write(s1_idx, Fill(nWays, tag), wmask)
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}
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// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
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.elsewhen (s0_valid) {
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@ -208,65 +209,59 @@ class ICache extends FrontendModule
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (refill_done && !invalidated) {
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vb_array := vb_array.bitSet(Cat(repl_way, s2_idx), Bool(true))
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vb_array := vb_array.bitSet(Cat(repl_way, s1_idx), Bool(true))
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}
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when (io.invalidate) {
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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val s2_disparity = Vec.fill(nWays){Bool()}
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val s1_disparity = Vec.fill(nWays){Bool()}
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for (i <- 0 until nWays)
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when (s2_valid && s2_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s2_idx), Bool(false)) }
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when (s1_valid && s1_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s1_idx), Bool(false)) }
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val s1_tag_match = Vec.fill(nWays){Bool()}
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val s2_tag_hit = Vec.fill(nWays){Bool()}
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val s2_dout = Vec.fill(nWays){Reg(Bits())}
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val s1_tag_hit = Vec.fill(nWays){Bool()}
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val s1_dout = Vec.fill(nWays){(Bits())}
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for (i <- 0 until nWays) {
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
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val s2_vb = Reg(Bool())
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val s2_tag_disparity = Reg(Bool())
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val s2_tag_match = Reg(Bool())
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val tag_out = tag_array(tag_raddr)(entagbits*(i+1)-1, entagbits*i)
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val s1_tag_disparity = code.decode(tag_out).error
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when (s1_valid && rdy && !stall) {
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s2_vb := s1_vb
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s2_tag_disparity := code.decode(tag_out).error
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s2_tag_match := s1_tag_match(i)
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}
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s1_tag_match(i) := tag_out(tagBits-1,0) === s1_tag
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s2_tag_hit(i) := s2_vb && s2_tag_match
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s2_disparity(i) := s2_vb && (s2_tag_disparity || code.decode(s2_dout(i)).error)
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s1_tag_hit(i) := s1_vb && s1_tag_match(i)
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s1_disparity(i) := s1_vb && (s1_tag_disparity || code.decode(s1_dout(i)).error)
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}
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s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
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s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_)
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for (i <- 0 until nWays) {
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val data_array = Mem(Bits(width = code.width(rowBits)), nSets*refillCycles, seqRead = true)
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val s1_raddr = Reg(UInt())
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when (narrow_grant.valid && repl_way === UInt(i)) {
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val e_d = code.encode(narrow_grant.bits.data)
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if(refillCycles > 1) data_array(Cat(s2_idx, refill_cnt)) := e_d
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else data_array(s2_idx) := e_d
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if(refillCycles > 1) data_array(Cat(s1_idx, refill_cnt)) := e_d
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else data_array(s1_idx) := e_d
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}
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// /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
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.elsewhen (s0_valid) {
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s1_raddr := s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
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}
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// if s1_tag_match is critical, replace with partial tag check
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when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
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s1_dout(i) := 0
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when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s1_dout(i) := data_array(s1_raddr) }
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}
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val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits)))(coreInstBits-1,0))
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
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// output signals
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io.resp.valid := s2_hit
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io.resp.valid := s1_hit
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io.mem.acquire.valid := (state === s_request)
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io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
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io.mem.acquire.bits := GetBlock(addr_block = refill_addr >> UInt(blockOffBits))
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// control state machine
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switch (state) {
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is (s_ready) {
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when (s2_miss) { state := s_request }
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when (s1_miss) { state := s_request }
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invalidated := Bool(false)
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}
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is (s_request) {
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