riscv/rocket-chip
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4f2e2480a8
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58 Commits

Author SHA1 Message Date
Andrew Waterman
4f2e2480a8 When exceptions occur in D-mode, set pc=0x808, not 0x800 
Closes #43
 2016-06-06 20:57:22 -07:00
Andrew Waterman
3b0c1ed0c3 Cope with changes to AddrMap 2016-06-03 13:50:29 -07:00
Andrew Waterman
9949347569 First stab at debug interrupts 2016-06-01 16:57:10 -07:00
Andrew Waterman
00ea9a7d82 Remove most of mstatus when user mode isn't supported 2016-05-25 15:37:32 -07:00
Andrew Waterman
335e2c8a1e Support disabling atomics extension 2016-05-24 15:05:41 -07:00
Howard Mao
5cbcc41515 get rid of unused imports 2016-05-02 18:23:46 -07:00
Andrew Waterman
f784f4da93 Rename PRCICoreIO to PRCITileIO 2016-05-02 18:08:01 -07:00
Andrew Waterman
000e20f937 Remove MIPI; make mip.MSIP read-only 
The PRCI block outside the core will provide IPIs eventually
 2016-05-02 15:18:41 -07:00
Andrew Waterman
83fa489cef Stop using HTIF CSR port 
The port itself is still present to keep other stuff compiling.
 2016-05-02 14:40:52 -07:00
Andrew Waterman
491184a8f8 ERET -> xRET; remove mcfgaddr 2016-04-30 17:32:51 -07:00
Andrew Waterman
cae4265f3b Change mcfgaddr pointer 2016-04-28 16:14:05 -07:00
Andrew Waterman
739cf07637 Remove mtime/mtimecmp 
The RTC is now a device that lives on the MMIO bus.
 2016-04-27 14:54:51 -07:00
Andrew Waterman
5fd5b58743 Remove stats CSR 2016-04-26 15:31:32 -07:00
Howard Mao
b7527268bb use address map instead of MMIOBase to find size of memory 2016-04-21 18:44:39 -07:00
Andrew Waterman
adb7eacf6e Fix Chisel3 build for XLen=32 2016-03-30 22:48:51 -07:00
Andrew Waterman
8ad8e8a691 Add partial Sv48/Sv57 support 
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
 2016-03-30 11:02:22 -07:00
Andrew Waterman
7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Andrew Waterman
82c595d11a Fix no-FPU elaboration of CSR file 2016-03-10 17:30:56 -08:00
Andrew Waterman
bc15e8649e WIP on priv spec v1.9 2016-03-02 23:29:58 -08:00
Howard Mao
78579672d3 make mtvec configurable and writeable 2016-01-29 14:51:56 -08:00
Howard Mao
305185c034 send DMA requests through MMIO and get responses through CSRs 2016-01-29 14:51:56 -08:00
Howard Mao
120361226d fix more Chisel3 deprecations 2016-01-14 14:46:31 -08:00
Andrew Waterman
00d17abd78 Don't ignore data value when writing MIPI 2016-01-12 16:23:06 -08:00
Andrew Waterman
5294e94794 Remove CSR back pressure ability 
We were using it for IPIs, but no longer need it.
 2015-11-24 18:28:14 -08:00
Andrew Waterman
0f092b9b59 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:51:43 -08:00
Yunsup Lee
c7235fecb5 further state optimization in CSRfile when not UseVM 2015-10-25 10:23:46 -07:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Henry Cook
1a1185be3f Vectorize ROCC and Tile memory interfaces 2015-10-20 15:02:24 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Andrew Waterman
f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Howard Mao
d89bcd3922 modify csr file to bring in line with HTIF changes 2015-09-22 10:10:57 -07:00
Christopher Celio
e22bf02a80 [commitlog] CSR's cycle optionally set to instret 
- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.
 2015-09-15 16:47:26 -07:00
Andrew Waterman
78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Andrew Waterman
6c0e1e33ab Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
Andrew Waterman
57930e8a26 Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
Andrew Waterman
049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares 
This one's hella ugly, but for the time being, idgaf.
 2015-07-28 02:48:49 -07:00
Andrew Waterman
f2dcc40e67 Chisel3 compatibility changes 2015-07-27 12:42:20 -07:00
Andrew Waterman
ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman
5362e2bbbd New machine-mode timer facility 2015-07-05 16:38:49 -07:00
Andrew Waterman
f460cb6c54 Update to privileged architecture 1.7 2015-05-19 02:32:21 -07:00
Christopher Celio
8fc2d38ca9 Removed unnecessary signal in CSRIO 2015-04-11 02:20:34 -07:00
Andrew Waterman
fe27b9b1b2 Support writing sstatus.fs even without an FPU 2015-04-04 15:20:18 -07:00
Andrew Waterman
faada5f110 Mask off LSBs of sepc/mepc/stvec 
Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.
 2015-03-25 00:20:58 -07:00
Andrew Waterman
90b31586ff Misc. CSR fixes/improvements 
- Support RV32 mstatus register
- Don't ignore mstatus.stie bit
- Support custom M-mode R/W CSRs for Raven chip
 2015-03-24 23:50:18 -07:00
Andrew Waterman
822698b567 support disabling supervisor mode (via UseVM parameter) 2015-03-24 19:32:45 -07:00
Andrew Waterman
66388be1ce Merge [shm]call into ecall, [shm]ret into eret 2015-03-17 02:24:41 -07:00
Andrew Waterman
2c875555a2 Separate exception return control from exception control 2015-03-17 00:14:32 -07:00
Andrew Waterman
e85c54cc4b New privileged ISA implementation 2015-03-14 02:49:07 -07:00
Henry Cook
741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
Andrew Waterman
cde7c9d869 simplify CSR decoding code 2014-10-03 14:31:26 -07:00