riscv/rocket-chip
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fix more Chisel3 deprecations

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This commit is contained in:
Howard Mao 2016-01-14 13:57:45 -08:00
parent d51c127646
commit 120361226d
9 changed files with 37 additions and 37 deletions
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2
rocket/src/main/scala/arbiter.scala
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@ -10,7 +10,7 @@ import junctions.ParameterizedBundle
class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
{
val io = new Bundle {
val requestor = Vec(new HellaCacheIO, n).flip
val requestor = Vec(n, new HellaCacheIO).flip
val mem = new HellaCacheIO
}

2
rocket/src/main/scala/btb.scala
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@ -46,7 +46,7 @@ class RAS(nras: Int) {
private val count = Reg(init=UInt(0,log2Up(nras+1)))
private val pos = Reg(init=UInt(0,log2Up(nras)))
private val stack = Reg(Vec(UInt(), nras))
private val stack = Reg(Vec(nras, UInt()))
}
class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {

10
rocket/src/main/scala/csr.scala
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@ -87,8 +87,8 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
val evec = UInt(OUTPUT, vaddrBitsExtended)
val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+retireWidth))
val uarch_counters = Vec(UInt(INPUT, log2Up(1+retireWidth)), 16)
val custom_mrw_csrs = Vec(UInt(INPUT, xLen), nCustomMrwCsrs)
val uarch_counters = Vec(16, UInt(INPUT, log2Up(1+retireWidth)))
val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
val cause = UInt(INPUT, xLen)
val pc = UInt(INPUT, vaddrBitsExtended)
val fatc = Bool(OUTPUT)
@ -149,11 +149,11 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
checkInterrupt(PRV_M, reg_mie.msip && reg_mip.msip, 0)
checkInterrupt(PRV_S, reg_mie.stip && reg_mip.stip, 1)
checkInterrupt(PRV_M, reg_mie.mtip && reg_mip.mtip, 1)
checkInterrupt(PRV_M, reg_fromhost != 0, 2)
checkInterrupt(PRV_M, reg_fromhost =/= 0, 2)
checkInterrupt(PRV_M, irq_rocc, 3)
val system_insn = io.rw.cmd === CSR.I
val cpu_ren = io.rw.cmd != CSR.N && !system_insn
val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
val host_csr_req_valid = Reg(Bool()) // don't reset
val host_csr_req_fire = host_csr_req_valid && !cpu_ren
@ -266,7 +266,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val csr_addr_priv = io.rw.addr(9,8)
val priv_sufficient = reg_mstatus.prv >= csr_addr_priv
val read_only = io.rw.addr(11,10).andR
val cpu_wen = cpu_ren && io.rw.cmd != CSR.R && priv_sufficient
val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R && priv_sufficient
val wen = cpu_wen && !read_only || host_csr_req_fire && host_csr_bits.rw
val wdata = Mux(io.rw.cmd === CSR.W, io.rw.wdata,
Mux(io.rw.cmd === CSR.C, io.rw.rdata & ~io.rw.wdata,

6
rocket/src/main/scala/fpu.scala
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@ -235,7 +235,7 @@ class FPToInt extends Module
when (io.in.valid) {
in := io.in.bits
when (io.in.bits.single && !io.in.bits.ldst && io.in.bits.cmd != FCMD_MV_XF) {
when (io.in.bits.single && !io.in.bits.ldst && io.in.bits.cmd =/= FCMD_MV_XF) {
in.in1 := in1_upconvert
in.in2 := in2_upconvert
}
@ -357,7 +357,7 @@ class FPToFP(val latency: Int) extends Module
val issnan2 = isnan2 && ~Mux(in.bits.single, in.bits.in2(22), in.bits.in2(51))
val minmax_exc = Cat(issnan1 || issnan2, Bits(0,4))
val isMax = in.bits.rm(0)
val isLHS = isnan2 || isMax != io.lt && !isnan1
val isLHS = isnan2 || isMax =/= io.lt && !isnan1
val mux = Wire(new FPResult)
mux.exc := minmax_exc
@ -539,7 +539,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
val memLatencyMask = latencyMask(mem_ctrl, 2)
val wen = Reg(init=Bits(0, maxLatency-1))
val winfo = Reg(Vec(Bits(), maxLatency-1))
val winfo = Reg(Vec(maxLatency-1, Bits()))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
val mem_winfo = Cat(mem_cp_valid, pipeid(mem_ctrl), mem_ctrl.single, mem_reg_inst(11,7)) //single only used for debugging

2
rocket/src/main/scala/frontend.scala
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@ -11,7 +11,7 @@ class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
val pc = UInt(width = vaddrBitsExtended) // ID stage PC
val data = Vec(Bits(width = coreInstBits), fetchWidth)
val data = Vec(fetchWidth, Bits(width = coreInstBits))
val mask = Bits(width = fetchWidth)
val xcpt_if = Bool()
}

4
rocket/src/main/scala/multiplier.scala
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@ -97,7 +97,7 @@ class MulDiv(
val nextMulReg = Cat(prod, mplier(mulw-1,unroll)).toUInt
val eOutMask = (SInt(BigInt(-1) << mulw) >> (count * unroll)(log2Up(mulw)-1,0))(mulw-1,0)
val eOut = Bool(earlyOut) && count != mulw/unroll-1 && count != 0 &&
val eOut = Bool(earlyOut) && count =/= mulw/unroll-1 && count =/= 0 &&
!isHi && (mplier & ~eOutMask) === UInt(0)
val eOutRes = (mulReg >> (mulw - count * unroll)(log2Up(mulw)-1,0))
val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
@ -136,7 +136,7 @@ class MulDiv(
isMul := cmdMul
isHi := cmdHi
count := 0
neg_out := !cmdMul && Mux(cmdHi, lhs_sign, lhs_sign != rhs_sign)
neg_out := !cmdMul && Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)
divisor := Cat(rhs_sign, rhs_in)
remainder := lhs_in
req := io.req.bits

26
rocket/src/main/scala/nbdcache.scala
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@ -330,7 +330,7 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
}
io.idx_match := (state != s_invalid) && idx_match
io.idx_match := (state =/= s_invalid) && idx_match
io.refill.way_en := req.way_en
io.refill.addr := (if(refillCycles > 1) Cat(req_idx, refill_cnt) else req_idx) << rowOffBits
io.tag := req.addr >> untagBits
@ -338,7 +338,7 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
val meta_hazard = Reg(init=UInt(0,2))
when (meta_hazard != UInt(0)) { meta_hazard := meta_hazard + 1 }
when (meta_hazard =/= UInt(0)) { meta_hazard := meta_hazard + 1 }
when (io.meta_write.fire()) { meta_hazard := 1 }
io.probe_rdy := !idx_match || (!states_before_refill.contains(state) && meta_hazard === 0)
@ -405,12 +405,12 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val sdq = Mem(sdqDepth, io.req.bits.data)
when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
val idxMatch = Wire(Vec(Bool(), nMSHRs))
val tagList = Wire(Vec(Bits(width = tagBits), nMSHRs))
val idxMatch = Wire(Vec(nMSHRs, Bool()))
val tagList = Wire(Vec(nMSHRs, Bits(width = tagBits)))
val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
val wbTagList = Wire(Vec(Bits(), nMSHRs))
val refillMux = Wire(Vec(new L1RefillReq, nMSHRs))
val wbTagList = Wire(Vec(nMSHRs, Bits()))
val refillMux = Wire(Vec(nMSHRs, new L1RefillReq))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
val mem_req_arb = Module(new LockingArbiter(
@ -690,7 +690,7 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val io = new Bundle {
val read = Decoupled(new L1DataReadReq).flip
val write = Decoupled(new L1DataWriteReq).flip
val resp = Vec(Bits(OUTPUT, encRowBits), nWays)
val resp = Vec(nWays, Bits(OUTPUT, encRowBits))
}
val waddr = io.write.bits.addr >> rowOffBits
@ -700,10 +700,10 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
for (w <- 0 until nWays by rowWords) {
val wway_en = io.write.bits.way_en(w+rowWords-1,w)
val rway_en = io.read.bits.way_en(w+rowWords-1,w)
val resp = Wire(Vec(Bits(width = encRowBits), rowWords))
val resp = Wire(Vec(rowWords, Bits(width = encRowBits)))
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (p <- 0 until resp.size) {
val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
array.write(waddr, data, wway_en.toBools)
@ -720,7 +720,7 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
} else {
for (w <- 0 until nWays) {
val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
when (io.write.bits.way_en(w) && io.write.valid) {
val data = Vec.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
array.write(waddr, data, io.write.bits.wmask.toBools)
@ -760,7 +760,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
val s2_killed = Reg(next=s1_valid && io.cpu.req.bits.kill)
val s2_req = Reg(io.cpu.req.bits)
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd =/= M_NOP
val s2_recycle = Wire(Bool())
val s2_valid_masked = Wire(Bool())
@ -893,9 +893,9 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
when (io.cpu.invalidate_lr) { lrsc_count := 0 }
val s2_data = Wire(Vec(Bits(width=encRowBits), nWays))
val s2_data = Wire(Vec(nWays, Bits(width=encRowBits)))
for (w <- 0 until nWays) {
val regs = Reg(Vec(Bits(width = encDataBits), rowWords))
val regs = Reg(Vec(rowWords, Bits(width = encDataBits)))
val en1 = s1_clk_en && s1_tag_eq_way(w)
for (i <- 0 until regs.size) {
val en = en1 && ((Bool(i == 0) || !Bool(doNarrowRead)) || s1_writeback)

4
rocket/src/main/scala/ptw.scala
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@ -54,7 +54,7 @@ class PTE(implicit p: Parameters) extends CoreBundle()(p) {
class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val requestor = Vec(new TLBPTWIO, n).flip
val requestor = Vec(n, new TLBPTWIO).flip
val mem = new HellaCacheIO
val dpath = new DatapathPTWIO
}
@ -85,7 +85,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val (pte_cache_hit, pte_cache_data) = {
val size = log2Up(pgLevels * 2)
val plru = new PseudoLRU(size)
val valid = Reg(Vec(Bool(), size))
val valid = Reg(Vec(size, Bool()))
val validBits = valid.toBits
val tags = Mem(size, UInt(width = paddrBits))
val data = Mem(size, UInt(width = ppnBits))

18
rocket/src/main/scala/tlb.scala
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@ -100,14 +100,14 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val tag_hit_addr = OHToUInt(tag_cam.io.hits)
// permission bit arrays
val valid_array = Reg(Vec(Bool(), entries)) // PTE is valid (not equivalent to CAM tag valid bit!)
val ur_array = Reg(Vec(Bool(), entries)) // user read permission
val uw_array = Reg(Vec(Bool(), entries)) // user write permission
val ux_array = Reg(Vec(Bool(), entries)) // user execute permission
val sr_array = Reg(Vec(Bool(), entries)) // supervisor read permission
val sw_array = Reg(Vec(Bool(), entries)) // supervisor write permission
val sx_array = Reg(Vec(Bool(), entries)) // supervisor execute permission
val dirty_array = Reg(Vec(Bool(), entries)) // PTE dirty bit
val valid_array = Reg(Vec(entries, Bool())) // PTE is valid (not equivalent to CAM tag valid bit!)
val ur_array = Reg(Vec(entries, Bool())) // user read permission
val uw_array = Reg(Vec(entries, Bool())) // user write permission
val ux_array = Reg(Vec(entries, Bool())) // user execute permission
val sr_array = Reg(Vec(entries, Bool())) // supervisor read permission
val sw_array = Reg(Vec(entries, Bool())) // supervisor write permission
val sx_array = Reg(Vec(entries, Bool())) // supervisor execute permission
val dirty_array = Reg(Vec(entries, Bool())) // PTE dirty bit
when (io.ptw.resp.valid) {
val pte = io.ptw.resp.bits.pte
tag_ram(r_refill_waddr) := pte.ppn
@ -137,7 +137,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val x_array = Mux(priv_s, sx_array.toBits, ux_array.toBits)
val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1)
val bad_va = io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
// it's only a store hit if the dirty bit is set
val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~Mux(io.req.bits.store, w_array, UInt(0)))
val tag_hit = tag_hits.orR