riscv/rocket-chip
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make mtvec configurable and writeable

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This commit is contained in:
Howard Mao 2016-01-29 11:32:59 -08:00
parent 7937fbf074
commit 78579672d3
4 changed files with 8 additions and 7 deletions
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6
rocket/src/main/scala/csr.scala
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@ -184,6 +184,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val cpuid = ((if (xLen == 32) BigInt(0) else BigInt(2)) << (xLen-2)) |
isa_string.map(x => 1 << (x - 'A')).reduce(_|_)
val impid = 1
val reg_mtvec = Reg(init = UInt(mtvecInit, xLen))
val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
CSRs.fflags -> (if (usingFPU) reg_fflags else UInt(0)),
@ -201,7 +202,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
CSRs.mstatus -> read_mstatus,
CSRs.mtdeleg -> UInt(0),
CSRs.mreset -> UInt(0),
CSRs.mtvec -> UInt(MTVEC),
CSRs.mtvec -> reg_mtvec,
CSRs.miobase -> UInt(p(junctions.MMIOBase)),
CSRs.mipi -> UInt(0),
CSRs.mip -> reg_mip.toBits,
@ -295,7 +296,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
when (some_interrupt_pending) { reg_wfi := false }
io.fatc := insn_sfence_vm
io.evec := Mux(io.exception || csr_xcpt, (reg_mstatus.prv << 6) + MTVEC,
io.evec := Mux(io.exception || csr_xcpt, (reg_mstatus.prv << 6) + reg_mtvec,
Mux(maybe_insn_redirect_trap, reg_stvec.sextTo(vaddrBitsExtended),
Mux(reg_mstatus.prv(1) || Bool(!p(UseVM)), reg_mepc, reg_sepc)))
io.ptbr := reg_sptbr
@ -427,6 +428,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_csr_req_fire) { reg_fromhost := wdata } }
when (decoded_addr(CSRs.mtohost)) { when (reg_tohost === UInt(0) || host_csr_req_fire) { reg_tohost := wdata } }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata & ~UInt("b11") }
if (usingVM) {
when (decoded_addr(CSRs.sstatus)) {
val new_sstatus = new SStatus().fromBits(wdata)

2
rocket/src/main/scala/frontend.scala
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@ -42,7 +42,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
val s1_same_block = Reg(Bool())
val s2_valid = Reg(init=Bool(true))
val s2_pc = Reg(init=UInt(START_ADDR))
val s2_pc = Reg(init=UInt(startAddr))
val s2_btb_resp_valid = Reg(init=Bool(false))
val s2_btb_resp_bits = Reg(btb.io.resp.bits)
val s2_xcpt_if = Reg(init=Bool(false))

4
rocket/src/main/scala/package.scala
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@ -2,7 +2,3 @@
package object rocket extends
rocket.constants.ScalarOpConstants
{
val MTVEC = 0x100
val START_ADDR = MTVEC + 0x100
}

3
rocket/src/main/scala/rocket.scala
View File

@ -22,6 +22,7 @@ case object CoreInstBits extends Field[Int]
case object CoreDataBits extends Field[Int]
case object CoreDCacheReqTagBits extends Field[Int]
case object NCustomMRWCSRs extends Field[Int]
case object MtvecInit extends Field[BigInt]
trait HasCoreParameters extends HasAddrMapParameters {
implicit val p: Parameters
@ -50,6 +51,8 @@ trait HasCoreParameters extends HasAddrMapParameters {
else p(BuildRoCC).flatMap(_.csrs)
val nRoccCsrs = p(RoccNCSRs)
val nCores = p(HtifKey).nCores
val mtvecInit = p(MtvecInit)
val startAddr = mtvecInit + 0x100
// Print out log of committed instructions and their writeback values.
// Requires post-processing due to out-of-order writebacks.