4c31248917
make sure UseAtomics is on when PTW is being used
2016-06-22 16:09:45 -07:00
d1c83ccda0
change Tile interface to allow arbitrary number of cached and uncached channels
2016-06-20 09:55:30 -07:00
60bddddfe6
Merge sptbr and sasid
2016-06-17 18:29:05 -07:00
0b4c8e9af7
Add D-mode single-step support
2016-06-15 16:21:24 -07:00
e3816d5fc7
set invalidate_lr in other rocc examples ( #47 )
...
This should fix https://travis-ci.org/ucb-bar/rocket-chip/jobs/137607305
2016-06-14 16:59:37 -07:00
e3b4b55836
Refactor breakpoints and support range comparison (currently disabled)
2016-06-10 19:55:58 -07:00
c8c7246cce
Update breakpoint spec
2016-06-09 19:07:21 -07:00
2c325151bf
pass invalidate_lr through simple cache interface ( #45 )
2016-06-09 17:22:36 -07:00
586c1079d0
Fix D$ for set size > page size
2016-06-09 13:02:28 -07:00
dca55a2b35
Respect breakpoint privilege settings
2016-06-09 12:41:52 -07:00
c85ea7b987
Set badaddr on breakpoints
2016-06-09 12:33:43 -07:00
4cd77cef10
Make dcsr.halt writable
2016-06-09 12:30:09 -07:00
8516e38eb2
remove implicit modulo addressing in FPU ( #44 )
2016-06-09 11:33:33 -07:00
e3c17b5f74
Add provisional breakpoint support
2016-06-08 20:19:52 -07:00
4f2e2480a8
When exceptions occur in D-mode, set pc=0x808, not 0x800
...
Closes #43
2016-06-06 20:57:22 -07:00
3b0c1ed0c3
Cope with changes to AddrMap
2016-06-03 13:50:29 -07:00
13386af1d1
Get rid of unused implicit conversion
2016-06-01 19:30:41 -07:00
9949347569
First stab at debug interrupts
2016-06-01 16:57:10 -07:00
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
3ee5144923
Fix TLB tag check logic when ASIDs are present
2016-05-27 12:24:17 -07:00
c104b57c52
Use BitPat implicit conversion in instruction decoder
2016-05-26 22:23:21 -07:00
96fa1eb6ad
Add UInt->BitPat implicit conversion
...
This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
2016-05-26 18:52:53 -07:00
0c50bfcfb3
Work around more zero-width wire cases
2016-05-25 21:47:48 -07:00
40f38dde63
Work around lack of zero-width wires in D$
2016-05-25 19:44:31 -07:00
00ea9a7d82
Remove most of mstatus when user mode isn't supported
2016-05-25 15:37:32 -07:00
5442b89664
Remove unnecessary muxes in RV32 MulDiv
2016-05-25 14:27:02 -07:00
9aa724706e
Don't include RV64 instructions in RV32 decode table
2016-05-25 14:26:45 -07:00
4605b616c1
Fix bug in D$ AMO/storegen logic
2016-05-24 16:26:07 -07:00
5dac7b818d
Support set associativity in blocking D$
2016-05-24 15:45:52 -07:00
e0addb5723
Support uncached AMOs in blocking D$
2016-05-24 15:45:35 -07:00
f14d87e327
Support larger I$ sets when VM is disabled
2016-05-24 15:44:59 -07:00
3b35c7470e
Add uncached support to blocking D$
2016-05-24 15:05:41 -07:00
42f079ce57
JAL requires DW_XPR
...
This has been benign so far because of how the logic minimization worked.
2016-05-24 15:05:41 -07:00
b92c73e361
Add LR/SC to blocking D$
2016-05-24 15:05:41 -07:00
0d93d1a1a0
Clean up pending store logic a bit
2016-05-24 15:05:41 -07:00
0b8de578d4
Add additional D$ store buffering to prevent structural hazards
2016-05-24 15:05:41 -07:00
354cb2d5ec
Don't stall I$ response when resolving a branch misprediction
...
This avoids a fetch bubble.
Not clear if this is the best way to do it. Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
2016-05-24 15:05:41 -07:00
d7790ac6a4
WIP on blocking D$
2016-05-24 15:05:41 -07:00
335e2c8a1e
Support disabling atomics extension
2016-05-24 15:05:41 -07:00
765b90f6a4
Stall on D$ lockups less conservatively
2016-05-24 15:05:41 -07:00
a3061047e3
Instantiate blocking D$ when NMSHRS=0
2016-05-24 15:05:41 -07:00
80482890fd
Don't rely on tag value for nacks
2016-05-24 15:05:41 -07:00
e19c5e5d2c
IOMSHR: support atomic operations
2016-05-24 15:00:50 -07:00
7bc38383de
add (non-working) blocking data cache
2016-05-20 18:59:05 -07:00
f228309bd1
add assertion to make sure SimpleHellaCacheIF doesn't get exception
2016-05-20 16:30:27 -07:00
4aef567a80
Fix MMIO bug: replay_next wasn't set
2016-05-13 17:59:53 -07:00
742c05d6a7
Pipeline D$->I$ control paths
...
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
2016-05-13 17:07:28 -07:00
8fa2de0816
chisel3 fix to RoCC connections honor last connect
2016-05-05 18:09:48 -07:00
9dd23a603a
Remove HTIF port
2016-05-03 13:41:58 -07:00
5352497edb
MPRV takes effect regardless of privilege mode
2016-05-02 19:53:25 -07:00
