16bfbda3c9
Refactor the TransactionTracker logic in all the L2 TileLink Managers.
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They now share common sub-transactions within traits, and use a common
set of state transitions and scoreboarding logic. Tracker allocation
logic has also been updated. No changes to external IOs or the TileLink protocol.
A new bufferless Broadcast hub is also included, but does not yet pass fuzzing checks.
2016-06-16 15:18:48 -07:00
2d2096e509
Add smaller ROM/RAM for 32-bit debug ( #60 )
2016-06-15 15:07:43 -07:00
e5cfc2dac1
Add a Smi to TileLink converter ( #59 )
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I'm trying to get someone to attach their stuff to Rocket Chip for the
upcoming tapout. TileLink sounded too complicated, but Smi went over
well. Since the mmioNetwork in Rocket Chip is based on TileLink, it
seemed like the easiest thing to do was to write a TileLink to Smi
converter so people could use it.
It turns out there was already one inside the groundtest unit tests, so
I just moved that into uncore (it was inlined into a test case so you
couldn't actually use it before). Internally the converter uses Nasti,
but I figured that's good enough for now.
2016-06-10 14:04:28 -07:00
cee0cf345e
[debug] Update Debug ROM contents to write F..F to RAM in case of exception
2016-06-09 14:05:30 -07:00
a1ebc73477
tilelink: don't accidentally make a malformed union
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Closes #55
2016-06-09 10:44:00 -07:00
31b72625aa
ahb: allow no-ops to progress also when a slave is !hready
2016-06-09 10:41:12 -07:00
7014eef339
ahb: fix bugs found using comparatortest
2016-06-09 10:41:11 -07:00
93c1b17b52
[debug] Remove erroneous buffer on SB read data ( #56 )
2016-06-08 23:31:13 -04:00
5151570894
Fix valid signal for multibeat grants
2016-06-08 15:13:39 -07:00
f421e2ab11
fix TileLinkWidthAdapter
2016-06-08 09:58:23 -07:00
324cabc494
tilelink: wmask was double the width it should be
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When amo_offset = UInt(0), UIntToOH(amo_offset) = "b01", not b"1".
This meant that the amo wmask was double wide, making wmask() fat.
2016-06-07 14:04:01 -07:00
2d66ac93d3
make sure HastiRAM cuts off the correct number of bits for word address
2016-06-06 09:26:51 -07:00
dd85f2410f
Avoid need for cloneType
2016-06-05 23:47:56 -07:00
631e3e2dd9
Make PRCI a singleton, not per-tile
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Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
2016-06-05 23:06:21 -07:00
be7500e4a9
Update PLIC addr map
2016-06-05 23:04:51 -07:00
b832689642
Correct Debug ROM contents
2016-06-05 19:35:25 -07:00
605fb5b92f
[debug]: fix issue with subword select logic
2016-06-05 19:31:07 -07:00
3e8322816b
Correct DMINFO Fields
2016-06-05 19:29:50 -07:00
7e550ab07c
[debug] rocket: fix for issue 121, correct debug ROM and stall logic
2016-06-05 19:29:44 -07:00
2e88ffc364
Cope with changes to AddrMap
2016-06-03 13:48:09 -07:00
f1745bf142
Allow PLIC nPriorities=0 (priority fixed at 1)
2016-06-02 13:48:29 -07:00
b7ca2145b3
Fix PLIC control bug when !grant.ready
2016-06-02 13:47:59 -07:00
0866b4c045
Can't assign to Vec literals
2016-06-01 23:36:34 -07:00
20e1de08da
Avoid chisel2 pitfall
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This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3. D'oh.
2016-06-01 23:35:49 -07:00
5629fb62bf
Avoid bitwise sub-assignment
2016-06-01 21:59:02 -07:00
9518b3d589
Fix arithmetic in ROM row count
2016-06-01 21:59:02 -07:00
8e80d1ec80
Avoid floating-point arithmetic where integers suffice
2016-06-01 21:59:02 -07:00
11b3cee07a
Ahb tweaks ( #50 )
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* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully
I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.
* ahb: optionally disable atomics => optimize to nothing
Trust the compiler the compiler to optimize away unused logic.
2016-06-01 16:42:39 -07:00
740a6073f6
Add Debug Module ( #49 )
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* Add Debug Module
* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents
* [debug] Update Debug ROM contents to match updated addresses
2016-06-01 16:33:33 -07:00
e8408f0a8a
fix HastiRAM
2016-06-01 10:33:59 -07:00
6d82c0d156
Add M_FLUSH_ALL command
2016-05-31 19:25:31 -07:00
8afdd7e3da
Work around PutBlocks draining into data array prematurely
2016-05-26 23:08:05 -07:00
391a9b9110
Use buses, rather than crossbars, by default in TLInterconnect
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We should eventually parameterize this, of course.
2016-05-26 16:10:42 -07:00
b6d26e90f8
Add generic TileLink width adapter
2016-05-26 15:59:42 -07:00
8139f71dfb
Work around Chisel2 bug
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This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
2016-05-26 12:37:31 -07:00
22568de5f3
Work around another zero-width wire limitation
2016-05-25 21:42:02 -07:00
e2755a0f0a
Work around zero-width wire limitation in HTIF
2016-05-25 20:39:53 -07:00
3e238adc67
rtc: fix acquire message type check
2016-05-25 20:37:48 -07:00
7f1792cba3
ahb: backport bridge to chisel2
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Closes #47
2016-05-25 13:40:24 -07:00
c49cb10c74
Merge pull request #42 from terpstra/ahb
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Ahb
2016-05-24 17:02:15 -07:00
88cc91db75
Ignore way_en in MetadataArray for direct-mapped caches
2016-05-24 15:47:09 -07:00
a012341d96
ahb: TileLink => AHB bridge, including atomics and bursts
2016-05-24 14:58:27 -07:00
ace9362d81
ahb: amoalu does not need so many parameters! (i want to reuse it)
2016-05-24 14:58:27 -07:00
00d31dc5c5
bram: use new hasti definitions
2016-05-24 13:35:16 -07:00
ee0acc1d07
Fix BRAM assertion condition
2016-05-23 13:19:53 -07:00
3e0b5d6fd9
Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,
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but would otherwise be allocated.
Closes #45
2016-05-20 16:35:30 -07:00
fd83d20857
Use a def instead of a lazy val in ManagerCoherenceAgent.
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Prevents C++ emulator from randomizing inputs in unit testing.
Closes #44
2016-05-20 16:31:12 -07:00
d69446e177
Add config classes to drive unit testing of L2 TileLink agents.
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Closes #43
2016-05-20 16:15:43 -07:00
4f84d8f757
make sure to hook up finish in ClientTileLinkEnqueuer
2016-05-18 13:13:34 -07:00
f138819992
fix order of assignments in ManagerTileLinkNetworkPort
2016-05-11 16:45:00 -07:00
