riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
250 Commits 1 Branch 0 Tags
008ad1f45bbe6bd8c7e6e3a1786a0046a737ec1f
Commit Graph
100 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman c38065d0e8 clean up priority encoders 2012-02-29 16:13:14 -08:00
Andrew Waterman b9ec69f8f5 add new Queue singleton 2012-02-29 14:21:42 -08:00
Andrew Waterman 012da6002e replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Andrew Waterman c99f6bbeb7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Andrew Waterman 2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman 1d41a41afa remove extraneous constants 2012-02-27 17:49:48 -08:00
Andrew Waterman 6e706c7c74 fix yet another AMO-related replay bug 2012-02-26 20:20:45 -08:00
Andrew Waterman e12b9eae93 remove ext_mem interface 
hindsight is 20/20
 2012-02-26 18:53:39 -08:00
Andrew Waterman 2d04664a98 simplify cpu-cache interface 2012-02-26 18:26:29 -08:00
Andrew Waterman ad713a5d83 fix icache ram depth; new chisel 2012-02-26 17:51:46 -08:00
Andrew Waterman 4121fb178c clean up mul/div interface; use VU mul if HAVE_VEC 2012-02-24 19:22:35 -08:00
Andrew Waterman b3a3289d34 fix (?) external memory request nack interface 2012-02-24 01:42:33 -08:00
Andrew Waterman 7b3cce79e3 allocate a primary miss on a prefetch 2012-02-23 22:40:24 -08:00
Andrew Waterman 012028efaa fix fpga build 2012-02-23 22:19:38 -08:00
Andrew Waterman 5332bab6f1 expose FMA ports outside of FPU (for the VU) 2012-02-23 17:39:34 -08:00
Andrew Waterman 6ceaa0e80a correct and simplify replay_next logic 2012-02-23 16:52:52 -08:00
Andrew Waterman f939088be1 move datapath control signals into control unit 
because that's where control signals go
 2012-02-23 16:52:52 -08:00
Andrew Waterman 7c929afe2b HTIF now controls CPU reset 2012-02-22 19:30:03 -08:00
Andrew Waterman 3eebf40310 nack CPU requests during any replay 2012-02-22 18:37:13 -08:00
Andrew Waterman cfd79c731b add resp_type to ext_mem interface 2012-02-21 17:42:00 -08:00
Andrew Waterman 9a80adef50 only instantiate VI$ if HAVE_VEC 2012-02-21 15:53:19 -08:00
Andrew Waterman c8f768c8b3 fix AMO replay bug 
like the recent AMO bug fix, but affects stores too.  oops.
 2012-02-21 14:39:54 -08:00
Andrew Waterman d5608b2728 fix AMO replay bug 
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
 2012-02-21 01:02:16 -08:00
Andrew Waterman 6135615104 unify cache backend interfaces; generify arbiter 2012-02-20 00:51:48 -08:00
Andrew Waterman 7034c9be65 new htif protocol and implementation 
You must update your fesvr and isasim!
 2012-02-19 23:15:45 -08:00
Andrew Waterman 9af86633d7 invalidate I$ prefetcher when invalidating I$ 2012-02-17 17:56:01 -08:00
Andrew Waterman 1b5e39e7fc fix bug in BTB 
a BTB update followed by a taken branch could cause incorrect control flow.
 2012-02-15 21:36:08 -08:00
Andrew Waterman fc5ba769da disable vector unit by default 2012-02-15 18:58:41 -08:00
Andrew Waterman 8b3b3abd3d fix external memory request nack logic 2012-02-15 18:57:40 -08:00
Andrew Waterman fe2c1d1321 add vec->ctrl fences 2012-02-15 18:31:19 -08:00
Andrew Waterman c13524ad3a fix vcmdq full replay logic 2012-02-15 17:49:12 -08:00
Andrew Waterman 0ec7767c13 declaring success on FPU for now 2012-02-14 19:11:57 -08:00
Andrew Waterman 297223a13c squash subsequent external mem request after nack 2012-02-14 15:12:16 -08:00
Andrew Waterman 38c67e5a9e add fmin.[s|d] and fmax.[s|d] 2012-02-14 06:37:18 -08:00
Andrew Waterman ee9fc10668 add fcvt.s.d, fcvt.d.s 2012-02-14 06:03:43 -08:00
Andrew Waterman ce202c73d1 add fsgnj[n|x].[s|d] 2012-02-14 04:24:35 -08:00
Andrew Waterman 1d604bcd49 remove top-level Makefile 
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
 2012-02-14 02:53:43 -08:00
Andrew Waterman 15dc2d8c40 add fp writeback arbitration logic 2012-02-14 00:32:25 -08:00
Andrew Waterman 0366465cb1 parameterize the scoreboards 2012-02-13 18:12:23 -08:00
Andrew Waterman 6c2d8a37ae remove a partial update that makes chisel barf 
chisel regards it as a combinational loop, even though it isn't.
 2012-02-13 16:45:29 -08:00
Andrew Waterman c78c738f60 minor cleanups 2012-02-13 03:13:49 -08:00
Andrew Waterman b5a19a54a3 add fcvt.[s|d].[w|l][u] 2012-02-13 02:01:26 -08:00
Andrew Waterman a4a9d2312c add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d] 2012-02-13 01:30:01 -08:00
Andrew Waterman 069037ff3a add FP recoding 2012-02-12 23:31:50 -08:00
Andrew Waterman 25ecfb9bbc clean up caches 
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
 2012-02-12 20:32:06 -08:00
Andrew Waterman 08b6517a23 add FP ops mftx, mxtf, mtfsr, mffsr 2012-02-12 20:12:53 -08:00
Andrew Waterman 9bb1558a34 WIP on FPU 2012-02-12 04:36:01 -08:00
Andrew Waterman 50a283d311 move store data generation into EX stage 
doing so removes it from the critical path of FP store unrecoding.
 2012-02-12 01:35:55 -08:00
Andrew Waterman 725190d0ee update to new chisel 2012-02-11 17:20:33 -08:00
Andrew Waterman f8b937d590 fix 32-bit divider bug 
thanks, torture!

also, tidied up the code a bit.
 2012-02-09 03:47:59 -08:00
Andrew Waterman 03ee49f424 fix 32-bit AMOs to upper halves of 64-bit words 
thanks, torture!
 2012-02-09 03:31:47 -08:00
Andrew Waterman 92493ad153 fix mul/div kill bug 
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
 2012-02-09 02:26:03 -08:00
Andrew Waterman 128ec567ed make BTB fully associative; don't use it for JALR 
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux.  the benfit
was close to nil, anyway.
 2012-02-09 01:34:00 -08:00
Andrew Waterman 8b6b0f5367 add external memory request interface for vec unit 2012-02-08 22:30:45 -08:00
Andrew Waterman 10b5a0006c fix mul/div to rd=0 2012-02-08 20:11:57 -08:00
Andrew Waterman a1855b12c2 clean up queues 2012-02-08 17:55:05 -08:00
Andrew Waterman 990e3a1b34 fix fpu port direction bug 2012-02-08 15:19:26 -08:00
Andrew Waterman b3f6f9a5fd fix BTB misprediction check for negative addresses 
also index BTB with PC, not PC+4
 2012-02-08 15:05:28 -08:00
Andrew Waterman e9da2cf66a improve id/ex datapath 
move operand selection into decode stage; simplify bypassing
 2012-02-08 06:47:26 -08:00
Andrew Waterman d471a8b2da arbitrate for LLFU writebacks in MEM stage 2012-02-08 04:21:05 -08:00
Andrew Waterman ebed56500e fix mul/wb hazard checks 
I erroneously assumed that those instructions set id_wen.
 2012-02-08 01:56:11 -08:00
Andrew Waterman 5403d069e9 add fp loads/stores 2012-02-07 23:54:25 -08:00
Andrew Waterman fde8e3b696 clean up bypassing/hazard checking a bit 2012-02-06 17:26:45 -08:00
Andrew Waterman 99a959e6b1 remove pc+4 piperegs and add new ex pc+4 adder 2012-02-02 13:33:27 -08:00
Andrew Waterman 01a156eb98 make # of dcache lines configurable 2012-02-01 21:11:45 -08:00
Andrew Waterman b1bbf56b74 clean up wb->id bypass 2012-02-01 16:41:18 -08:00
Andrew Waterman 38c9105ea1 fix mul/div deadlock bug 
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
 2012-01-30 21:14:28 -08:00
Andrew Waterman bd241ea237 fix when badvaddr is set 2012-01-30 17:15:42 -08:00
Andrew Waterman a96c92f58d enable amomin[u]/amomax[u 2012-01-26 20:45:04 -08:00
Andrew Waterman a7999d4525 don't flush I$ unless fence.i commits 
otherwise, we might not make forward progress.
 2012-01-26 20:37:09 -08:00
Andrew Waterman 41855a6d47 fix missing "otherwise" in PCR file 
this fixes timer interrupts for VLSI backend.
 2012-01-26 19:33:55 -08:00
Andrew Waterman 9e6b86fe85 Fix a nasty replay bug 
If a mispredicted branch was followed by an instruction dependent
on a load that missed in the cache, the mispredicted path would
be executed rather than the correct path. Fail.

Example broken code:

lw   x2, 0(x2)          # cache miss
beq  x3, x0, somewhere  # mispredicted branch
move x4, x2             # wrong-path instruction dependent on load miss
 2012-01-24 03:40:01 -08:00
Andrew Waterman 06fdf79dab fix long-latency writeback arbitration bug 2012-01-24 00:56:47 -08:00
Andrew Waterman f1c355e3cd check pc/effective address sign extension 2012-01-24 00:15:17 -08:00
Andrew Waterman a5a020f97b update chisel and remove SRAM_READ_LATENCY 2012-01-23 20:59:38 -08:00
Andrew Waterman e7bf07d55e fix AMO replay bug 2012-01-23 15:35:53 -08:00
Andrew Waterman 31c56228e2 add missing "otherwise" 2012-01-21 20:13:15 -08:00
Andrew Waterman addfe55735 add FPGA memory generator script 2012-01-13 18:19:08 -08:00
Andrew Waterman 20aee36c96 move PCR writes to WB stage 2012-01-02 15:42:39 -08:00
Andrew Waterman 3045b33460 remove second RF write port 
load miss writebacks are treated like mul/div now.
 2012-01-02 02:51:30 -08:00
Andrew Waterman ffe23a1ee8 fix WAW hazard handling 2012-01-02 00:25:11 -08:00
Andrew Waterman eb657dd250 reduce superfluous replays 
we only replay after a cache miss if we mis-scheduled the use of a load.
 2012-01-01 21:28:38 -08:00
Andrew Waterman efc623cc36 validate BTB address and use BTB for J/JAL/JR/JALR 
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
 2012-01-01 17:04:14 -08:00
Andrew Waterman 2f8fcebea0 remove datapath register resets resets 2012-01-01 16:09:40 -08:00
Andrew Waterman f9160c53cf fixes for correct verilog generation 2011-12-29 23:46:21 -08:00
Andrew Waterman 1028ff7d9b fix multiplier bug 2011-12-29 23:45:09 -08:00
Andrew Waterman d65e1a2eee vlsi verilog compiles now but doesn't simulate 2011-12-20 22:08:27 -08:00
Andrew Waterman 38ea10a5f4 parameterized multiplier unrolling 2011-12-20 04:18:28 -08:00
Andrew Waterman 733fc8e65e booth multiplier 2011-12-20 03:49:07 -08:00
Andrew Waterman b5a8b6dc73 fix divider for RV32 2011-12-19 16:57:53 -08:00
Andrew Waterman bcceb08373 add dummy mul_rdy signal 2011-12-17 07:30:47 -08:00
Andrew Waterman 96c78829b4 improve ALU and fix revealed emulator bug 2011-12-17 07:20:32 -08:00
Andrew Waterman 82700cad72 fix multiplier for rv32 2011-12-17 07:20:00 -08:00
Andrew Waterman a8d0cd95e6 hellacache now works 2011-12-17 03:26:11 -08:00
Andrew Waterman 56c4f44c2a hellacache returns! 
but AMOs are unimplemented.
 2011-12-12 06:49:39 -08:00
Andrew Waterman 8308345364 work in progress on hellacache 2011-12-10 07:01:47 -08:00
Andrew Waterman ce201559f3 Support cache->cpu nacks one cycle after request 2011-12-10 00:42:09 -08:00
Andrew Waterman c01e1f1cef Don't replay from EX stage. 
EX replays are now handled from MEM.  We may move them to WB.
 2011-12-09 19:42:58 -08:00
Andrew Waterman 218f63e66e code cleanup/parameterization 2011-12-09 00:42:43 -08:00
Andrew Waterman a87ad06780 Automatically infer rocketCAM address width 2011-12-06 02:05:40 -08:00