clean up queues
This commit is contained in:
Andrew Waterman
parent
990e3a1b34
commit
a1855b12c2
@ -23,7 +23,7 @@ class ioIPrefetcher extends Bundle() {
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class rocketIPrefetcher extends Component() {
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val io = new ioIPrefetcher();
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val pdq = (new queueSimplePF(REFILL_CYCLES)) { Bits(width = MEM_DATA_BITS) };
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val pdq = (new queue(REFILL_CYCLES, flushable = true)) { Bits(width = MEM_DATA_BITS) };
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val s_invalid :: s_valid :: s_refilling :: s_req_wait :: s_resp_wait :: s_bad_resp_wait :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_invalid);
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@ -43,9 +43,6 @@ class rocketIPrefetcher extends Component() {
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io.mem.req_tag := !(io.icache.req_val && !hit);
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io.mem.req_addr := Mux(io.mem.req_tag(0).toBool, prefetch_addr, io.icache.req_addr);
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val pdq_reset = Reg(resetVal = Bool(true));
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pdq_reset <== demand_miss & ~hit | (state === s_bad_resp_wait);
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val fill_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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when (ip_mem_resp_val.toBool) { fill_cnt <== fill_cnt + UFix(1); }
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val fill_done = (~fill_cnt === UFix(0)) & ip_mem_resp_val;
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@ -59,7 +56,7 @@ class rocketIPrefetcher extends Component() {
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io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag(0).toBool) || (forward && pdq.io.deq.valid);
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io.icache.resp_data := Mux(forward, pdq.io.deq.bits, io.mem.resp_data);
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pdq.io.q_reset := pdq_reset;
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pdq.io.flush := Reg(demand_miss && !hit || (state === s_bad_resp_wait), resetVal = Bool(false))
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pdq.io.enq.bits := io.mem.resp_data;
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pdq.io.enq.valid := ip_mem_resp_val.toBool;
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pdq.io.deq.ready := forward;
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@ -197,8 +197,7 @@ class MSHR(id: Int) extends Component {
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val next_dirty = dirty || io.req_sec_val && io.req_sec_rdy && !req_load
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val sec_rdy = io.idx_match && !refilled && (dirty || !requested || req_load)
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val rpq = (new queueSimplePF(NRPQ)) { new RPQEntry() }
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rpq.io.q_reset := Bool(false)
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val rpq = (new queue(NRPQ)) { new RPQEntry() }
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
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rpq.io.enq.bits.offset := io.req_offset
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rpq.io.enq.bits.cmd := io.req_cmd
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@ -419,7 +418,7 @@ class WritebackUnit extends Component {
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val mem_req_data = Bits(MEM_DATA_BITS, OUTPUT)
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}
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val wbq = (new queueSimplePF(REFILL_CYCLES)) { Bits(width = MEM_DATA_BITS) }
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val wbq = (new queue(REFILL_CYCLES)) { Bits(width = MEM_DATA_BITS) }
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val valid = Reg(resetVal = Bool(false))
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val cnt = Reg() { UFix(width = log2up(REFILL_CYCLES+1)) }
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val addr = Reg() { new WritebackReq() }
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@ -430,7 +429,6 @@ class WritebackUnit extends Component {
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val block_refill = valid && ((io.refill_req.bits.addr(IDX_BITS-1,0) === addr.idx) || (cnt === UFix(REFILL_CYCLES)))
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val refill_val = io.refill_req.valid && !block_refill
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wbq.io.q_reset := Bool(false)
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wbq.io.enq.valid := valid && Reg(io.data_req.valid && io.data_req.ready)
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wbq.io.enq.bits := io.data_resp
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wbq.io.deq.ready := io.mem_req.ready && !refill_val && (cnt === UFix(REFILL_CYCLES))
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@ -1,226 +1,45 @@
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package Top
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{
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import Chisel._
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import Node._;
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import scala.math._;
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class ioQueueCtrl(addr_sz: Int) extends Bundle()
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class ioQueue[T <: Data](flushable: Boolean)(data: => T) extends Bundle
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{
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val q_reset = Bool(INPUT);
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val enq_val = Bool(INPUT);
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val enq_rdy = Bool(OUTPUT);
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val deq_val = Bool(OUTPUT);
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val deq_rdy = Bool(INPUT);
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val wen = Bool(OUTPUT);
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val waddr = UFix(addr_sz, OUTPUT);
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val raddr = UFix(addr_sz, OUTPUT);
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val flush = if (flushable) Bool(INPUT) else null
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val enq = new ioDecoupled()(data)
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val deq = new ioDecoupled()(data).flip
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}
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class queueCtrl(entries: Int) extends Component
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class queue[T <: Data](entries: Int, flushable: Boolean = false)(data: => T) extends Component
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{
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val addr_sz = log2up(entries)
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override val io = new ioQueueCtrl(addr_sz);
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val io = new ioQueue(flushable)(data)
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// Enqueue and dequeue pointers
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val enq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
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val deq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
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val maybe_full = Reg(resetVal = Bool(false))
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val enq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val deq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val full = Reg(width = 1, resetVal = Bool(false));
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io.deq.valid := maybe_full || enq_ptr != deq_ptr
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io.enq.ready := !maybe_full || enq_ptr != deq_ptr
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io.waddr := enq_ptr;
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io.raddr := deq_ptr;
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val do_enq = io.enq.ready && io.enq.valid
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val do_deq = io.deq.ready && io.deq.valid
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// We enq/deq only when they are both ready and valid
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val do_enq = io.enq_rdy && io.enq_val;
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val do_deq = io.deq_rdy && io.deq_val;
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// Determine if we have pipeline or flowthrough behaviour and
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// set the write enable accordingly.
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val empty = ~full && (enq_ptr === deq_ptr);
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io.wen := do_enq;
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// Ready signals are calculated from full register. If pipeline
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// behavior is enabled, then the enq_rdy signal is also calculated
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// combinationally from the deq_rdy signal. If flowthrough behavior
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// is enabled then the deq_val signal is also calculated combinationally
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// from the enq_val signal.
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io.enq_rdy := ~full;
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io.deq_val := ~empty;
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// Control logic for the enq/deq pointers and full register
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val deq_ptr_inc = deq_ptr + UFix(1, 1);
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val enq_ptr_inc = enq_ptr + UFix(1, 1);
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val deq_ptr_next =
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Mux(do_deq, deq_ptr_inc,
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deq_ptr);
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val enq_ptr_next =
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Mux(do_enq, enq_ptr_inc,
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enq_ptr);
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val full_next =
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Mux(do_enq && ~do_deq && ( enq_ptr_inc === deq_ptr ), Bool(true),
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Mux(do_deq && full, Bool(false),
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full));
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when (io.q_reset) {
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enq_ptr <== UFix(0, addr_sz);
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deq_ptr <== UFix(0, addr_sz);
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full <== Bool(false);
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if (flushable) {
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when (io.flush) {
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deq_ptr <== UFix(0)
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enq_ptr <== UFix(0)
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maybe_full <== Bool(false)
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}
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}
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otherwise {
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enq_ptr <== enq_ptr_next;
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deq_ptr <== deq_ptr_next;
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full <== full_next;
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when (do_deq) {
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deq_ptr <== deq_ptr + UFix(1)
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}
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}
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class ioQueueSimplePF[T <: Data]()(data: => T) extends Bundle
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{
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val q_reset = Bool(INPUT);
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val enq = new ioDecoupled()(data)
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val deq = new ioDecoupled()(data).flip
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}
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class queueSimplePF[T <: Data](entries: Int)(data: => T) extends Component
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{
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override val io = new ioQueueSimplePF()(data);
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val ctrl = new queueCtrl(entries);
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ctrl.io.q_reset <> io.q_reset;
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ctrl.io.deq_val <> io.deq.valid;
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ctrl.io.enq_rdy <> io.enq.ready;
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ctrl.io.enq_val <> io.enq.valid;
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ctrl.io.deq_rdy <> io.deq.ready;
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val ram = Mem(entries, ctrl.io.wen, ctrl.io.waddr, io.enq.bits);
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ram.read(ctrl.io.raddr) <> io.deq.bits;
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}
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// TODO: SHOULD USE INHERITANCE BUT BREAKS INTROSPECTION CODE
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// class IOqueueCtrlFlow extends IOqueueCtrl
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class ioQueueCtrlFlow(addr_sz: Int) extends Bundle() /* IOqueueCtrl */
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{
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val enq_val = Bool(INPUT);
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val enq_rdy = Bool(OUTPUT);
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val deq_val = Bool(OUTPUT);
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val deq_rdy = Bool(INPUT);
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val wen = Bool(OUTPUT);
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val waddr = UFix(addr_sz, OUTPUT);
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val raddr = UFix(addr_sz, OUTPUT);
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val flowthru = Bool(OUTPUT);
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}
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class queueCtrlFlow(entries: Int) extends Component
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{
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val addr_sz = log2up(entries)
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override val io = new ioQueueCtrlFlow(addr_sz);
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// Enqueue and dequeue pointers
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val enq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val deq_ptr = Reg(width = addr_sz, resetVal = UFix(0, addr_sz));
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val full = Reg(width = 1, resetVal = Bool(false));
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io.waddr := enq_ptr;
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io.raddr := deq_ptr;
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// We enq/deq only when they are both ready and valid
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val do_enq = io.enq_rdy && io.enq_val;
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val do_deq = io.deq_rdy && io.deq_val;
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// Determine if we have pipeline or flowthrough behaviour and
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// set the write enable accordingly.
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val empty = ~full && (enq_ptr === deq_ptr);
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val do_flowthru = empty && do_enq && do_deq;
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io.flowthru := do_flowthru;
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io.wen := do_enq && ~do_flowthru;
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// Ready signals are calculated from full register. If pipeline
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// behavior is enabled, then the enq_rdy signal is also calculated
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// combinationally from the deq_rdy signal. If flowthrough behavior
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// is enabled then the deq_val signal is also calculated combinationally
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// from the enq_val signal.
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io.enq_rdy := ~full;
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io.deq_val := ~empty || ( empty && io.enq_val );
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// Control logic for the enq/deq pointers and full register
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val deq_ptr_inc = deq_ptr + UFix(1, 1);
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val enq_ptr_inc = enq_ptr + UFix(1, 1);
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val deq_ptr_next =
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Mux(do_deq && ~do_flowthru, deq_ptr_inc,
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deq_ptr);
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val enq_ptr_next =
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Mux(do_enq && ~do_flowthru, enq_ptr_inc,
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enq_ptr);
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val full_next =
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Mux(do_enq && ~do_deq && ( enq_ptr_inc === deq_ptr ), Bool(true),
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Mux(do_deq && full, Bool(false),
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full));
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enq_ptr <== enq_ptr_next;
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deq_ptr <== deq_ptr_next;
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full <== full_next;
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}
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class ioQueueDpathFlow[T <: Data](addr_sz: Int)(data: => T) extends Bundle()
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{
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val wen = Bool(INPUT);
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val flowthru = Bool(INPUT);
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val deq_bits = data.asOutput;
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val enq_bits = data.asInput;
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val waddr = UFix(addr_sz, INPUT);
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val raddr = UFix(addr_sz, INPUT);
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}
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class queueDpathFlow[T <: Data](entries: Int)(data: => T) extends Component
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{
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val addr_sz = log2up(entries)
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override val io = new ioQueueDpathFlow(addr_sz)(data);
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val ram = Mem(entries, io.wen, io.waddr, io.enq_bits);
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val rout = ram(io.raddr);
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Mux(io.flowthru, io.enq_bits, rout) <> io.deq_bits;
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}
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class ioQueueFlowPF[T <: Data](data: => T) extends Bundle()
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{
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val enq_val = Bool(INPUT);
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val enq_rdy = Bool(OUTPUT);
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val enq_bits = data.asInput;
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val deq_val = Bool(OUTPUT);
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val deq_rdy = Bool(INPUT);
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val deq_bits = data.asOutput;
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}
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class queueFlowPF[T <: Data](entries: Int)(data: => T) extends Component
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{
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override val io = new ioQueueFlowPF(data);
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val ctrl = new queueCtrlFlow(entries);
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val dpath = new queueDpathFlow(entries)(data);
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ctrl.io.deq_rdy <> io.deq_rdy;
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ctrl.io.wen <> dpath.io.wen;
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ctrl.io.raddr <> dpath.io.raddr;
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ctrl.io.waddr <> dpath.io.waddr;
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ctrl.io.flowthru <> dpath.io.flowthru;
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ctrl.io.enq_val <> io.enq_val;
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dpath.io.enq_bits <> io.enq_bits;
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ctrl.io.deq_val <> io.deq_val;
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ctrl.io.enq_rdy <> io.enq_rdy;
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dpath.io.deq_bits <> io.deq_bits;
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}
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when (do_enq) {
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enq_ptr <== enq_ptr + UFix(1)
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}
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when (do_enq != do_deq) {
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maybe_full <== do_enq
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}
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Mem(entries, do_enq, enq_ptr, io.enq.bits).read(deq_ptr) <> io.deq.bits
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}
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