riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix 32-bit AMOs to upper halves of 64-bit words

Browse Source 
thanks, torture!
This commit is contained in:
Andrew Waterman 2012-02-09 03:30:55 -08:00
parent f47d888feb
commit 03ee49f424
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/nbdcache.scala
View File

@ -635,11 +635,13 @@ class AMOALU extends Component {
val less = Mux(cmp_lhs === cmp_rhs, cmp_diff, Mux(sgned, cmp_lhs, cmp_rhs))
val cmp_out = Mux(min === less, io.lhs, io.rhs)
io.out := Mux(io.cmd === M_XA_ADD, adder_out,
val out = Mux(io.cmd === M_XA_ADD, adder_out,
Mux(io.cmd === M_XA_SWAP, io.rhs,
Mux(io.cmd === M_XA_AND, io.lhs & io.rhs,
Mux(io.cmd === M_XA_OR, io.lhs | io.rhs,
/* MIN[U]/MAX[U] */ cmp_out))));
io.out := Mux(word, Cat(out(31,0), out(31,0)).toUFix, out)
}
class HellaCacheDM extends Component {