Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
9e6b86fe85
If a mispredicted branch was followed by an instruction dependent on a load that missed in the cache, the mispredicted path would be executed rather than the correct path. Fail. Example broken code: lw x2, 0(x2) # cache miss beq x3, x0, somewhere # mispredicted branch move x4, x2 # wrong-path instruction dependent on load miss |
||
|---|---|---|
| rocket/src/main/scala | ||