riscv/rocket-chip
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  • f8f29c69b8 MetaData & friends moved to uncore/ Henry Cook 2014-04-23 16:24:20 -0700
  • fc825c7103 MetaData & friends moved to uncore/ Henry Cook 2014-04-23 16:23:51 -0700
  • f4d326b8d7 Prep in HellaCache for extracting MetaData to uncore Henry Cook 2014-04-23 15:43:31 -0700
  • 83a3cb4999 bump rocket, uncore Henry Cook 2014-04-22 17:32:39 -0700
  • 39681303b8 beginning of l2 cache Henry Cook 2014-04-22 16:55:35 -0700
  • 5c62cff2ce put replacement policy in uncore and minor nbdcache cleanups Henry Cook 2014-04-22 16:53:20 -0700
  • 2fefbdd453 fixes to physical design flow Yunsup Lee 2014-04-21 21:36:39 -0700
  • cfd6748318 patches to make FAME1/dram IOs compile with up-to-date chisel (bumped) Henry Cook 2014-04-21 17:26:33 -0700
  • 1bf5439f0b include new mm test in benchmarks Henry Cook 2014-04-18 18:05:30 -0700
  • 5613dc7d1b replaced Lists with Vecs Henry Cook 2014-04-16 18:14:12 -0700
  • 09e2ec1f9e Fix sign of remainder when dividing by zero Andrew Waterman 2014-04-18 16:30:25 -0700
  • bf2ff7804e Add chisel-dependent.sbt for -DchiselVersion="latest.release" Jim Lawson 2014-04-17 17:01:40 -0700
  • 1fa505f9ff remove superfluous AVec object Henry Cook 2014-04-16 17:19:08 -0700
  • 3520620fbd Remove D$ -> BTB path Andrew Waterman 2014-04-15 23:05:02 -0700
  • de492b3cf7 Fix critical path through integer scoreboard Andrew Waterman 2014-04-15 21:26:54 -0700
  • e4c97e7a57 push tools/tests Yunsup Lee 2014-04-14 21:18:22 -0700
  • 691aa4107e bump rocket Henry Cook 2014-04-14 17:13:57 -0700
  • 444d0449e3 io.cnt bug in serializer Henry Cook 2014-04-14 17:12:30 -0700
  • 2cb4dbae39 Refactored uncore constants and tilelink data Henry Cook 2014-04-10 13:19:50 -0700
  • 5a5f69bfca finished uncore constant/tilelink data refactor Henry Cook 2014-04-10 13:13:46 -0700
  • b1df49ba30 removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants Henry Cook 2014-04-01 17:14:45 -0700
  • fbca7c6bb3 refactor ioMem and associcated constants. merge Aqcuire and AcquireData Henry Cook 2014-03-29 10:53:49 -0700
  • 1da8ef2ddf Added serdes to decouple cache row size from tilelink data size Henry Cook 2014-04-07 18:22:46 -0700
  • 910b3b203a removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants Henry Cook 2014-04-01 17:15:46 -0700
  • ebdc0a2692 merge Aqcuire and AcquireData. cache line size coupled to tilelink data size Henry Cook 2014-03-29 10:59:07 -0700
  • cac04afc25 Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL. Stephen Twigg 2014-04-08 22:14:16 -0700
  • f643d38672 Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required) Stephen Twigg 2014-04-08 16:50:52 -0700
  • e90f2484aa Sync with riscv-opcodes (csr register mapping) Stephen Twigg 2014-04-08 15:48:37 -0700
  • fb8c7d3da5 Push rocket Andrew Waterman 2014-04-07 23:49:06 -0700
  • 3ed8adf032 Add early out for MUL[W] (not MULH[[S]U]) Andrew Waterman 2014-04-07 23:48:02 -0700
  • 927287da34 Bypass RAS push/pop Andrew Waterman 2014-04-07 23:47:53 -0700
  • 817517c663 Better branch prediction Andrew Waterman 2014-04-07 16:08:06 -0700
  • f235fa0db6 Move branch resolution to M stage Andrew Waterman 2014-04-07 15:58:49 -0700
  • db59fc65ab Add return address stack Andrew Waterman 2014-04-01 15:01:27 -0700
  • 56f515c255 first steps in uncore constant/tilelink data refactor Henry Cook 2014-03-30 08:13:05 -0700
  • e3b12e0b85 Make BTB more complexity-effective Andrew Waterman 2014-03-25 05:22:04 -0700
  • 804b09c8c5 Frontend QoR tweaks Andrew Waterman 2014-03-25 05:20:24 -0700
  • 6465e2df14 Make Int -> Bool conversions explicit Andrew Waterman 2014-03-24 04:36:53 -0700
  • 1b030777ce Remove vestigial control signal Andrew Waterman 2014-03-24 04:36:12 -0700
  • 16274a84b6 update fpga testbench Donggyu Kim 2014-03-21 16:21:15 -0700
  • a228dbfa0d Revert "Update library dependencies (jenkins builds)" Jim Lawson 2014-03-20 10:40:05 -0700
  • 8d68ea9e0b Merge branch 'master' of github.com:ucb-bar/reference-chip Yunsup Lee 2014-03-20 01:46:30 -0700
  • 7bbcf920be sync up master Yunsup Lee 2014-03-20 01:45:23 -0700
  • 51808d9982 Fix minor FP bugs Andrew Waterman 2014-03-18 18:37:53 -0700
  • 5996418021 Fix exception behavior of fmin/fmax Andrew Waterman 2014-03-18 18:36:19 -0700
  • dec98eb047 Update library dependencies (jenkins builds) Jim Lawson 2014-03-18 11:37:08 -0700
  • d2c32b048a fix bug in htif_fini, need to use vc_handle! Yunsup Lee 2014-03-18 01:35:08 -0700
  • 0d124d283a Write our own vcs main() routine Andrew Waterman 2014-03-17 17:02:28 -0700
  • 7f23257873 Print out random seed if test fails Andrew Waterman 2014-03-17 15:35:17 -0700
  • fcbbb275aa Fix nondeterminism Andrew Waterman 2014-03-15 17:35:30 -0700
  • 54cbf0c4f1 Add (unused) RV32 CSRs Andrew Waterman 2014-03-15 17:33:17 -0700
  • 943d7ac80a Use LinkedHashSet/Map for simpler determinism Andrew Waterman 2014-03-15 17:31:48 -0700
  • 53d62cb69d remove nondeterminism Donggyu Kim 2014-03-15 16:45:58 -0700
  • e4b56b5d0e generate verilog for rekall Yunsup Lee 2014-03-15 15:31:04 -0700
  • b6bf7cfe0c push chisel Andrew Waterman 2014-03-11 23:56:57 -0700
  • 7ac003a4f7 push hardfloat Andrew Waterman 2014-03-11 20:36:39 -0700
  • f04bde75fb New FP encoding Andrew Waterman 2014-03-11 19:12:20 -0700
  • a0389645b7 New FP encoding; improved FP implementation Andrew Waterman 2014-03-11 18:58:24 -0700
  • 00bc1a2293 Add fclass.{s|d} instructions Andrew Waterman 2014-03-10 16:59:07 -0700
  • 6951333a08 push rocket Yunsup Lee 2014-03-04 23:43:00 -0800
  • ac4b3f9f22 print out core id Yunsup Lee 2014-03-04 23:38:49 -0800
  • d055c0ebaf Push rocket/hardfloat/chisel Andrew Waterman 2014-03-04 16:38:34 -0800
  • 9f2e16c58a Fix D$ arbiter for >2 inputs Andrew Waterman 2014-03-04 16:32:17 -0800
  • fa75f6e81e Fix null pointer exception when HAS_FPU=false Andrew Waterman 2014-03-04 16:32:09 -0800
  • 23045ec379 add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv Yunsup Lee 2014-03-02 03:38:06 -0800
  • 49f0e43ed1 push riscv-tools Yunsup Lee 2014-03-01 03:31:03 -0800
  • e20d50436a committed in the wrong directory, meant to commit in the hwacha directory Yunsup Lee 2014-03-01 00:01:35 -0800
  • 8c459df3b6 flush deck when xcpt occurs, fixes remaining p test bugs Yunsup Lee 2014-02-28 22:50:34 -0800
  • cb14baab88 Reformatted hammer directory, added parent scripts to repo, as well as README. Adam Izraelevitz 2014-02-28 15:57:46 -0800
  • c7110c8389 Make FPU pipeline depths configurable Andrew Waterman 2014-02-28 13:39:35 -0800
  • 0c4442c172 push tests/tools Yunsup Lee 2014-02-27 20:28:19 -0800
  • bcfcdefe88 update hwacha Yunsup Lee 2014-02-27 04:39:12 -0800
  • 46714c0c60 more improvements to hwacha Yunsup Lee 2014-02-26 21:20:53 -0800
  • a5625de3d5 support vector irq tests Yunsup Lee 2014-02-25 21:18:03 -0800
  • fcfc1078f8 Merge branch 'master' of github.com:ucb-bar/reference-chip Ben Keller 2014-02-25 15:54:19 -0800
  • 220076506c push hwacha; all vector p/v/pt tests work now Yunsup Lee 2014-02-25 03:51:15 -0800
  • e5c2bd5e7b add extensions option to riscv-dis for better disassembly Yunsup Lee 2014-02-25 03:50:32 -0800
  • 98b830201a add wen signal to dasm printf Yunsup Lee 2014-02-25 03:31:06 -0800
  • 8acc9510c4 push hwacha,chisel Yunsup Lee 2014-02-24 01:43:55 -0800
  • 22345dd073 push rocket,hwacha Yunsup Lee 2014-02-22 22:53:24 -0800
  • 97b1841fcf change dcache tag bits to 7 Yunsup Lee 2014-02-22 22:53:04 -0800
  • f14f386b4f Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-02-19 15:50:28 -0800
  • a006bffca4 Merge branch 'master' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-02-19 15:04:03 -0800
  • 58d2e62e3f Merge branch 'master' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-02-19 14:24:36 -0800
  • de965d558a Renumber uarch CSRs into custom CSR space Andrew Waterman 2014-02-14 17:40:58 -0800
  • e554f6728d Update chisel Andrew Waterman 2014-02-12 18:40:05 -0800
  • 8e3ca609f7 Renumber uarch CSRs into custom CSR space Andrew Waterman 2014-02-14 17:40:00 -0800
  • 755293d785 Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha). Stephen Twigg 2014-02-14 10:12:09 -0800
  • 02dbd6b0aa Don't assign to your own inputs Andrew Waterman 2014-02-12 18:39:40 -0800
  • 6808245bb5 Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. Stephen Twigg 2014-02-12 16:50:13 -0800
  • e5de170215 Update Chisel, fixing Verilog backend Andrew Waterman 2014-02-12 14:28:43 -0800
  • e25c54e998 Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-02-12 13:52:24 -0800
  • c1e544886f Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-02-12 13:35:12 -0800
  • 1a03a64572 Merge branch 'dse' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-02-12 12:44:30 -0800
  • aae5f465c1 Merge branch 'master' of github.com:ucb-bar/reference-chip into dse Adam Izraelevitz 2014-02-11 17:31:55 -0800
  • 548cf16061 Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse Adam Izraelevitz 2014-02-11 14:36:47 -0800
  • 0ebb115a3c Revert to old AUIPC definition Andrew Waterman 2014-02-10 19:05:14 -0800
  • a09ff9fdc7 Revert to old AUIPC definition Andrew Waterman 2014-02-10 19:04:42 -0800
  • cda46b3ce1 use --recursive to populate all submodules. with current instructions you can't run tests because riscv-tests/env isn't pulled in Scott Beamer 2014-02-06 16:20:48 -0800
  • 1456170c6d Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence Andrew Waterman 2014-02-06 12:01:49 -0800