riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

flush deck when xcpt occurs, fixes remaining p test bugs

This commit is contained in:
Yunsup Lee 2014-02-28 22:50:34 -08:00
parent 0c4442c172
commit 8c459df3b6
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
riscv-tools

@ -1 +1 @@
Subproject commit 116e2f99b5d6b2174a89e69672049230a3bdc5f9
Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d

2
src/main/scala/RocketChip.scala
View File

@ -258,7 +258,7 @@ class Top extends Module {
val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU
//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
)
val io = new VLSITopIO(HTIF_WIDTH)