riscv/rocket-chip
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remove nondeterminism

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This commit is contained in:
Donggyu Kim 2014-03-15 16:45:58 -07:00
parent a0389645b7
commit 53d62cb69d
2 changed files with 13 additions and 2 deletions
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8
rocket/src/main/scala/ctrl.scala
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@ -412,7 +412,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
val id_csr_en = id_csr != CSR.N
val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr)
val legal_uint_csrs = new scala.collection.mutable.ArrayBuffer[Bits]
for (csr <- legal_csrs) {
legal_uint_csrs += UInt(csr)
}
val id_csr_invalid = id_csr_en && !Vec(legal_uint_csrs).contains(id_csr_addr)
val id_csr_privileged = id_csr_en &&
(id_csr_addr(11,10) === UInt(3) && id_csr_wen ||
id_csr_addr(11,10) === UInt(2) ||

7
rocket/src/main/scala/dpath_util.scala
View File

@ -243,7 +243,12 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
for (i <- 0 until reg_uarch_counters.size)
read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
val decoded_mapping = new scala.collection.mutable.ArrayBuffer[(Bool, Bits)]
for ((k, v) <- read_mapping) {
decoded_mapping += ((decoded_addr(k), v))
}
io.rw.rdata := Mux1H(decoded_mapping)
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {