generate verilog for rekall
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@ -31,7 +31,8 @@ object BuildSettings extends Build {
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lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
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lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
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lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket)
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lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha)
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lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel)
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lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall)
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val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
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val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")
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