Howard Mao
3e105eb352
make sure MixedAllocPutRegression uses a block that hasn't been cached already
2016-06-13 18:17:48 -07:00
Howard Mao
fe8d81958f
fix groundtests to fit new way of parameterizing TileLink clients
2016-06-13 16:17:27 -07:00
Howard Mao
a921458758
add a regression test for no-alloc Put following an alloc Put
2016-06-13 16:17:27 -07:00
Andrew Waterman
e3b4b55836
Refactor breakpoints and support range comparison (currently disabled)
2016-06-10 19:55:58 -07:00
Palmer Dabbelt
82cef6fa7b
Make a TileLink to Smi converter availiable to users ( #136 )
...
See the cooresponding uncore commit for details.
2016-06-10 18:49:17 -07:00
Palmer Dabbelt
0c695d8e83
Use the new TileLink to Smi converter ( #10 )
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I pulled out the TileLink to Smi converter and put it in uncore so I can
use it for my own stuff.
2016-06-10 14:04:48 -07:00
Palmer Dabbelt
e5cfc2dac1
Add a Smi to TileLink converter ( #59 )
...
I'm trying to get someone to attach their stuff to Rocket Chip for the
upcoming tapout. TileLink sounded too complicated, but Smi went over
well. Since the mmioNetwork in Rocket Chip is based on TileLink, it
seemed like the easiest thing to do was to write a TileLink to Smi
converter so people could use it.
It turns out there was already one inside the groundtest unit tests, so
I just moved that into uncore (it was inlined into a test case so you
couldn't actually use it before). Internally the converter uses Nasti,
but I figured that's good enough for now.
2016-06-10 14:04:28 -07:00
Andrew Waterman
b79db89c03
Update breakpoint spec
2016-06-09 19:13:55 -07:00
Andrew Waterman
c8c7246cce
Update breakpoint spec
2016-06-09 19:07:21 -07:00
Colin Schmidt
2c325151bf
pass invalidate_lr through simple cache interface ( #45 )
2016-06-09 17:22:36 -07:00
Wesley W. Terpstra
70d92995df
TestConfigs: add comparator config
2016-06-09 15:43:13 -07:00
Wesley W. Terpstra
3e51a8bb7a
submodules: include new ComparatorTile
2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764
fix groundtest tilelink xacts
2016-06-09 15:42:44 -07:00
Megan Wachs
cee0cf345e
[debug] Update Debug ROM contents to write F..F to RAM in case of exception
2016-06-09 14:05:30 -07:00
Wesley W. Terpstra
5562241a50
comparator: a new TileLink stress-tester
2016-06-09 14:02:35 -07:00
Andrew Waterman
586c1079d0
Fix D$ for set size > page size
2016-06-09 13:02:28 -07:00
Andrew Waterman
dca55a2b35
Respect breakpoint privilege settings
2016-06-09 12:41:52 -07:00
Andrew Waterman
c85ea7b987
Set badaddr on breakpoints
2016-06-09 12:33:43 -07:00
Andrew Waterman
4cd77cef10
Make dcsr.halt writable
2016-06-09 12:30:09 -07:00
Colin Schmidt
8516e38eb2
remove implicit modulo addressing in FPU ( #44 )
2016-06-09 11:33:33 -07:00
Wesley W. Terpstra
a1ebc73477
tilelink: don't accidentally make a malformed union
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Closes #55
2016-06-09 10:44:00 -07:00
Wesley W. Terpstra
31b72625aa
ahb: allow no-ops to progress also when a slave is !hready
2016-06-09 10:41:12 -07:00
Wesley W. Terpstra
7014eef339
ahb: fix bugs found using comparatortest
2016-06-09 10:41:11 -07:00
Colin Schmidt
40b6e44816
name resetSignal parameter to tile constructor
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if the tile constructor were to change groundtest
only needs to be updated if resetSignal is removed or renamed
2016-06-09 10:20:48 -07:00
Andrew Waterman
9e86b9efc9
Add provisional breakpoint support
2016-06-08 22:34:19 -07:00
Scott Johnson
73ed4ea07b
grammar
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English major I'm not, but my sister was and she says 'who' is correct here
2016-06-08 22:34:14 -07:00
mwachs5
93c1b17b52
[debug] Remove erroneous buffer on SB read data ( #56 )
2016-06-08 23:31:13 -04:00
Andrew Waterman
e3c17b5f74
Add provisional breakpoint support
2016-06-08 20:19:52 -07:00
Howard Mao
21feeb4a4f
have multiple outstanding requests in CacheFillTest
2016-06-08 19:53:42 -07:00
Wesley W. Terpstra
ed9fcea7f8
hasti: correct fix to locking
2016-06-08 16:28:30 -07:00
Wesley W. Terpstra
ad4e4f19be
Revert "Don't rely on Mux1H output when no inputs are hot"
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This reverts commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970.
2016-06-08 16:28:30 -07:00
Wesley W. Terpstra
3393d4362b
hasti: fix test SRAM depth
2016-06-08 16:28:30 -07:00
Howard Mao
65b62a9e5f
unbreak the emulator
2016-06-08 15:38:39 -07:00
Howard Mao
40ab0a7960
fix TL width adapter and make it easier to switch inner data width
2016-06-08 15:38:39 -07:00
Howard Mao
a809a1712a
make sure clocks and reset signals get intialized properly
2016-06-08 15:38:39 -07:00
Albert Ou
5151570894
Fix valid signal for multibeat grants
2016-06-08 15:13:39 -07:00
Howard Mao
0969be8804
Revert "make sure SlowIO clock divider is initialized on reset"
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This reverts commit 546aaad8cfb03e45e068733c2b694232bcf9dcdb.
2016-06-08 13:45:30 -07:00
Howard Mao
636a46c052
make sure SlowIO clock divider is initialized on reset
2016-06-08 10:02:21 -07:00
Howard Mao
f421e2ab11
fix TileLinkWidthAdapter
2016-06-08 09:58:23 -07:00
Donggyu Kim
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
Howard Mao
08e53a00f0
bump cde for better match failure stack trace
2016-06-07 16:15:10 -07:00
Howard Mao
2cd897e240
Revert "include the unmatched field in CDEMatchError"
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This reverts commit ff2937a788
2016-06-07 16:13:01 -07:00
Wesley W. Terpstra
324cabc494
tilelink: wmask was double the width it should be
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When amo_offset = UInt(0), UIntToOH(amo_offset) = "b01", not b"1".
This meant that the amo wmask was double wide, making wmask() fat.
2016-06-07 14:04:01 -07:00
Howard Mao
8db27a36c4
fix Tile reset power on behavior
2016-06-07 11:06:38 -07:00
Palmer Dabbelt
e6c4372332
Fix "make run-asm-tests" for Chisel 3
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This was just a missing Makefrag-verilog dependency (the .d file).
2016-06-06 21:36:55 -07:00
Andrew Waterman
2c17f828b6
bump chisel and rocket
2016-06-06 21:36:51 -07:00
Wesley W. Terpstra
5495705acf
Configs: enable AHB for FPGAs
2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33
RocketChip: handle atomics only if needed
2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf
RocketChip: add ahb mem interface
2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2
RocketChip: rename mem to mem_axi in preparation for new bus type
2016-06-06 21:35:55 -07:00
