riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman a999c055ed Don't take an interrupt when EX stage PC is invalid 
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch.  EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.

h/t Yunsup
 2014-09-11 01:46:52 -07:00
Andrew Waterman 81c752de84 Support disabling virtual memory 2013-09-24 13:58:47 -07:00
Andrew Waterman adc386f889 Turn off virtual memory inside RoCC base class 2013-09-24 13:58:47 -07:00
Andrew Waterman 1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Andrew Waterman 25ab402932 swap JAL, JALR encodings 2013-09-15 04:29:06 -07:00
Andrew Waterman 110e53cb48 Revert "Add early out to multiplier" 
This broke recently and I don't have time to figure out why.
 2013-09-15 04:15:32 -07:00
Andrew Waterman 88d1c47665 don't disassemble within chisel 2013-09-15 04:14:45 -07:00
Andrew Waterman f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman 18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman a0cb711451 Start adding RoCC 2013-09-14 15:31:50 -07:00
Andrew Waterman d053bdc89f Remove Hwacha from Rocket 
Soon it will use the coprocessor interface.
 2013-09-12 22:34:38 -07:00
Andrew Waterman 1edb1e2a0a Ignore LSB of PC 2013-09-12 17:55:58 -07:00
Andrew Waterman 59f5358435 Implement AQ/RL; move fence logic out of cache 2013-09-12 16:07:30 -07:00
Andrew Waterman 243c4ae342 sync up rocket with new isa 2013-09-12 03:44:38 -07:00
Andrew Waterman 95dd0d8be1 Remove DebugIO/error mode 2013-09-11 20:15:21 -07:00
Andrew WatermanandYunsup Lee b9f6e1a7ec Don't update BTB when garbage was fetched 2013-08-26 14:53:04 -07:00
Andrew Waterman 3895b75a56 Support non-power-of-2 BTBs; prefer invalid entries 2013-08-24 17:33:11 -07:00
Andrew Waterman daf23b8f79 Add early out to multiplier 2013-08-24 14:44:23 -07:00
Andrew Waterman 67f80ba4b2 Stall div/mul writeback until WB slot is free 2013-08-24 14:44:17 -07:00
Andrew Waterman d1b5076fee Don't update BTB when garbage was fetched 2013-08-24 14:44:11 -07:00
Andrew Waterman 52e31f3298 Bypass scoreboard updates 
This reduces div/mul/D$ miss latency by 1 cycle.
 2013-08-24 14:44:04 -07:00
Andrew Waterman d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Andrew Waterman 7cc53c7725 clean up Str 2013-06-15 00:45:53 -07:00
Andrew Waterman 95c5147dc5 Add RISC-V instruction disassembler 2013-06-13 10:31:04 -07:00
Andrew Waterman fe9adfe71b Simplify and correct integer multiplier 2013-05-22 17:27:50 -07:00
Andrew Waterman 28f914c3f2 don't JALR to speculatively-bypassed addresses 
Technically not necessary, but probably improves performance.
 2013-05-21 16:56:58 -07:00
Andrew Waterman 3a1b5f01b2 don't take interrupts while they're disabled! 
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
 2013-05-19 23:27:47 -07:00
Andrew Waterman 6eb4c2542a comment out I$ assert for now 2013-05-18 18:09:23 -07:00
Andrew Waterman 1dab984231 use UFix instead of Bits for arithmetic 2013-05-18 00:45:29 -07:00
Andrew Waterman dfa7a03f73 use assert, not Assert 2013-05-18 00:45:13 -07:00
Andrew Waterman d405ffa949 assume all I$ grants bear data 2013-05-01 21:01:20 -07:00
Andrew Waterman 474d321cc7 fix meta hazard counter to reset on new meta writes 2013-05-01 16:35:24 -07:00
Andrew Waterman a6a88fce19 Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle" 
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
 2013-05-01 16:34:45 -07:00
Andrew Waterman 63a38e7982 Revert "temp" 
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
 2013-05-01 16:34:33 -07:00
Andrew Waterman 1501e90c1f interlock probe unit on tag RAW hazards 2013-04-30 00:38:22 -07:00
Andrew Waterman 50ccc20bf3 replace RDNPC with AUIPC 2013-04-22 04:20:15 -07:00
Andrew Waterman ae7720e284 guarantee LR/SC forward progress 
the mechanism is to block new probes for several cycles after a successful LR.

this also cleans up the MSHR <-> ProbeUnit interface slightly.
 2013-04-07 19:27:21 -07:00
Andrew Waterman e74e032c87 simplify MSHR memory response logic 2013-04-06 01:03:37 -07:00
Andrew Waterman 1abb9277db fix LR/SC atomicity violation 
note, it's still not starvation-free.
 2013-04-05 19:13:38 -07:00
Andrew Waterman 8cbdeb2abf add LR/SC support 2013-04-04 17:07:09 -07:00
Andrew Waterman fc46daecf6 don't flush pipeline on writes to side-effect-free PCRs 
notably, K0, K1, and EPC
 2013-04-04 17:07:09 -07:00
Andrew Waterman 8b439ef20d only support setpcr/clearpcr of SR 
the full PCR RMW support was wasted area/power
 2013-04-04 17:07:08 -07:00
Andrew Waterman d43f484feb take interrupts on nonzero fromhost values 2013-04-04 17:07:08 -07:00
Andrew Waterman d4a3351cfc expose pending interrupts in status register 2013-04-04 17:07:08 -07:00
Andrew Waterman 35349d227f update to new Mem style 2013-02-20 16:09:46 -08:00
Andrew Waterman 9f89c812b7 fix HTIF memory size reporting 2013-01-29 23:08:25 -08:00
Andrew Waterman 66eb3720a4 fix SRAM semantics bug in HellaFlowQueue 2013-01-29 21:16:42 -08:00
Andrew Waterman 6275e009f8 fix HellaQueue deq.valid signal 2013-01-28 20:57:43 -08:00
Andrew Waterman 45d8066f45 add HellaQueue, an SRAM-based queue 2013-01-28 20:54:25 -08:00
Andrew Waterman 37c67f1d87 pipeline reset to the vector unit 2013-01-28 17:56:32 -08:00
Andrew Waterman c890099e09 add System Control Register space to HTIF 2013-01-24 23:41:24 -08:00
Andrew Waterman 575bd3445a re-generalize scoreboard 2013-01-24 18:00:39 -08:00
Andrew Waterman 1fbc20450e don't allow simultaneous reads and writes to the tag ram 2013-01-24 17:55:00 -08:00
Andrew Waterman 37ee843b2c don't use reset combinationally 2013-01-24 17:55:00 -08:00
Andrew Waterman bb6fbddf1f don't probe the mshr file to inquire about refills 2013-01-24 17:54:59 -08:00
Andrew Waterman 5b9f938263 correctly sign-extend badvaddr, epc, and ebase 2013-01-24 17:54:59 -08:00
Andrew Waterman 667b4ee858 remove Queue flush port (override reset instead) 2012-08-22 13:39:19 -07:00
Andrew Waterman d4a001b867 add PriorityMux; use to implement PriorityEncoder 2012-08-22 13:38:25 -07:00
Andrew Waterman 743e032f06 generalize interface to DecodeLogic 2012-08-22 13:38:07 -07:00
Andrew Waterman 80c243469e add flow queues and skid buffers 
hopefully they work
 2012-07-30 18:47:12 -07:00
Andrew Waterman 2ec76390e3 improve PriorityEncoderOH and add Counter util 2012-07-30 16:06:55 -07:00
Andrew Waterman 7778802395 reduce number of outstanding transactions 2012-07-26 14:51:41 -07:00
Andrew Waterman e496cd7584 use Mem to implement queues to speed things up 2012-07-13 21:48:05 -07:00
Andrew Waterman bac82762d3 use only one (wide) tag ram for set assoc. caches 2012-07-12 14:50:12 -07:00
Andrew Waterman 429fcbed8e fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman f645fb4dd7 add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00