Don't take an interrupt when EX stage PC is invalid
It was possible to take an interrupt on the instruction in the shadow of a short forward branch. EPC would thus get the wrong value, and so a wrong-path instruction would be executed upon return from interrupt. h/t Yunsup
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@ -240,7 +240,7 @@ class Datapath extends Module
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Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst),
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Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4)))
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val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(params(VAddrBits)-1,0)), mem_br_target)
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io.ctrl.mem_misprediction := mem_npc != Mux(io.ctrl.ex_valid, ex_reg_pc, id_pc)
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io.ctrl.mem_misprediction := mem_npc != ex_reg_pc || !io.ctrl.ex_valid
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io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1
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val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata)
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