generalize interface to DecodeLogic
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0f20771664
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743e032f06
@ -57,8 +57,8 @@ object Constants
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val DIV_RU = UFix(3, 2);
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val X = Bits("b?", 1)
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val N = UFix(0, 1);
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val Y = UFix(1, 1);
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val N = Bits(0, 1);
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val Y = Bits(1, 1);
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val WA_X = X
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val WA_RD = N
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@ -13,32 +13,32 @@ object DecodeLogic
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new Term(b.value)
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}
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}
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def logic(addr: Bits, keys: Seq[Bits], cache: scala.collection.mutable.Map[Term,Bits], terms: Set[Term]) = {
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def logic(addr: Bits, cache: scala.collection.mutable.Map[Term,Bits], terms: Set[Term]) = {
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terms.map { t =>
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if (!cache.contains(t))
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cache += t -> ((if (t.mask == 0) addr else addr & Lit(BigInt(2).pow(addr.width)-(t.mask+1), addr.width){Bits()}) === Lit(t.value, addr.width){Bits()})
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cache(t)
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}.foldLeft(Bool(false))(_||_)
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}
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def apply(addr: Bits, default: List[Bits], mapping: Array[(Bits, List[Bits])]) = {
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def apply(addr: Bits, default: Iterable[Bits], mapping: Iterable[(Bits, Iterable[Bits])]) = {
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var map = mapping
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var cache = scala.collection.mutable.Map[Term,Bits]()
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default map { d =>
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val dlit = d.litOf
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val dterm = term(dlit)
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val (keys, values) = map.unzip
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val keysterms = keys.map(k => term(k.litOf)) zip values.map(v => term(v.head.litOf))
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val keysterms = keys.toList.map(k => term(k.litOf)) zip values.toList.map(v => term(v.head.litOf))
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val result = (0 until math.max(dlit.width, values.map(_.head.litOf.width).max)).map({ case (i: Int) =>
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if (((dterm.mask >> i) & 1) != 0) {
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var mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1).toSet
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var maxt = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1).toSet
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logic(addr, keys, cache, SimplifyDC(mint, maxt, addr.width)).toBits
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logic(addr, cache, SimplifyDC(mint, maxt, addr.width)).toBits
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} else {
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val want = 1 - ((dterm.value.toInt >> i) & 1)
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val mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == want }.map(_._1).toSet
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val dc = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1).toSet
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val bit = logic(addr, keys, cache, Simplify(mint, dc, addr.width)).toBits
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val bit = logic(addr, cache, Simplify(mint, dc, addr.width)).toBits
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if (want == 1) bit else ~bit
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}
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}).reverse.reduceRight(Cat(_,_))
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