add System Control Register space to HTIF
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575bd3445a
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c890099e09
@ -36,6 +36,15 @@ class HTIFIO(ntiles: Int) extends Bundle
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val ipi_rep = (new FIFOIO) { Bool() }.flip
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}
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class SCRIO extends Bundle
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{
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val n = 64
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val rdata = Vec(n) { Bits(INPUT, 64) }
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val wen = Bool(OUTPUT)
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val waddr = UFix(OUTPUT, log2Up(n))
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val wdata = Bits(OUTPUT, 64)
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}
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class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Component with ClientCoherenceAgent
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{
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implicit val lnConf = conf.ln
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@ -43,6 +52,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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val host = new HostIO(w)
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val cpu = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles).flip }
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val mem = new TileLinkIO()(conf.ln)
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val scr = new SCRIO
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}
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val short_request_bits = 64
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@ -82,7 +92,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
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val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
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val pcr_coreid = if (conf.ln.nTiles == 1) UFix(0) else addr(20+log2Up(conf.ln.nTiles),20)
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val pcr_coreid = addr(log2Up(conf.ln.nTiles+1)-1+20,20)
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val pcr_wdata = packet_ram(0)
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val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
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@ -204,7 +214,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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io.mem.grant_ack.bits.header.src := UFix(conf.ln.nTiles)
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io.mem.grant_ack.bits.header.dst := UFix(0)
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val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
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val pcrReadData = Reg{Bits(width = io.cpu(0).pcr_rep.bits.getWidth)}
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for (i <- 0 until conf.ln.nTiles) {
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val my_reset = Reg(resetVal = Bool(true))
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val my_ipi = Reg(resetVal = Bool(false))
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@ -235,22 +245,37 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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when (cmd === cmd_writecr) {
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my_reset := pcr_wdata(0)
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}
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pcrReadData(i) := my_reset.toBits
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pcrReadData := my_reset.toBits
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state := state_tx
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}
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cpu.pcr_rep.ready := Bool(true)
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when (cpu.pcr_rep.valid) {
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pcrReadData(i) := cpu.pcr_rep.bits
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pcrReadData := cpu.pcr_rep.bits
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state := state_tx
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}
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}
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val scr_rdata = Vec(io.scr.rdata.size){Bits(width = 64)}
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for (i <- 0 until scr_rdata.size)
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scr_rdata(i) := io.scr.rdata(i)
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scr_rdata(0) := conf.ln.nTiles
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scr_rdata(1) := UFix(REFILL_CYCLES*MEM_DATA_BITS/8) << x_init.io.enq.bits.addr.getWidth
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io.scr.wen := false
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io.scr.wdata := pcr_wdata
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io.scr.waddr := pcr_addr.toUFix
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when (state === state_pcr_req && pcr_coreid === Fix(-1)) {
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io.scr.wen := cmd === cmd_writecr
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pcrReadData := scr_rdata(pcr_addr)
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state := state_tx
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}
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val tx_cmd = Mux(nack, cmd_nack, cmd_ack)
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val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
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val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext)
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val tx_data = Mux(tx_word_count === UFix(0), tx_header,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcrReadData(pcr_coreid),
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcrReadData,
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packet_ram(packet_ram_raddr)))
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io.host.in.ready := state === state_rx
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