riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

take interrupts on nonzero fromhost values

Browse Source
This commit is contained in:
Andrew Waterman 2013-03-25 23:27:23 -07:00
parent d4a3351cfc
commit d43f484feb
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/dpath_util.scala
View File

@ -178,7 +178,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
val wdata = Mux(io.w.en, io.w.data, host_pcr_bits.data)
io.status := reg_status
io.status.ip := Cat(r_irq_timer, Bool(false), r_irq_ipi, Bool(false),
io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
Bool(false), Bool(false), Bool(false), Bool(false))
io.ptbr_wen := wen && waddr === PTBR
io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix