Andrew Waterman
2c875555a2
Separate exception return control from exception control
2015-03-17 00:14:32 -07:00
Andrew Waterman
e85c54cc4b
New privileged ISA implementation
2015-03-14 02:49:07 -07:00
Yunsup Lee
ebbd14254c
uncached port should be a HeaderlessUncachedTileLinkIO type
2015-03-13 02:12:23 -07:00
Henry Cook
51e4cd7616
Added UncachedTileLinkIO port to RocketTile, simplify arbitration
2015-03-12 16:30:04 -07:00
Yunsup Lee
ea018b3d84
stall rocket decode when not rocc ready
2015-03-11 22:33:03 -07:00
Colin Schmidt
e293d89035
fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
2015-03-10 10:28:05 -07:00
Henry Cook
95aa295c39
Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
2015-03-09 16:34:43 -07:00
Henry Cook
b36d751250
sret bugfix: bypass arbiter
2015-03-05 13:14:16 -08:00
Christopher Celio
06dea3790a
Removed sret from ptw; sret now comes thru io.cpu to dcache
2015-03-03 16:50:41 -08:00
Christopher Celio
5d07733057
Removed TLBPTWIO from the io.cpu bundle for icache/dcache
2015-03-03 16:40:39 -08:00
Henry Cook
1e0c16c557
new metadata api
2015-02-28 17:00:32 -08:00
Henry Cook
0b131173e6
WritebackUnit multibeat control logic bugfix
2015-02-16 10:59:57 -08:00
Henry Cook
aa46b8b72d
Slightly refactor TLBResp
2015-02-03 19:32:37 -08:00
Stephen Twigg
3d35ccd401
Explicitely convert results of Bits Muxes to UInt
...
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:10:54 -08:00
Henry Cook
741e6b77ad
Rename some params, use refactored TileLink
2015-02-01 20:37:31 -08:00
Scott Beamer
00e074cdd9
fixes slight bug for non-power of 2 number of ras entries
2015-01-29 15:29:25 -08:00
Andrew Waterman
a98127c09e
Merge branch 'ss-frontend'
2015-01-04 20:26:38 -08:00
Andrew Waterman
b70f7683d3
Merge branch 'master' into ss-frontend
...
Conflicts:
src/main/scala/ctrl.scala
2015-01-04 19:59:18 -08:00
Andrew Waterman
87ad1a5703
More control cleanup
2015-01-04 19:46:01 -08:00
Andrew Waterman
2aee85cb11
Flush pipeline from MEM stage
...
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control. But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
2015-01-04 16:40:16 -08:00
Andrew Waterman
94b75c7cb1
Continue refactoring control
2015-01-04 15:32:05 -08:00
Andrew Waterman
6181de4cc9
Much refactor, so control
2015-01-03 13:34:38 -08:00
Henry Cook
1cb65d5ec1
%s/master/manager/g
2014-12-29 22:56:18 -08:00
Henry Cook
77e5e6b561
refill bug
2014-12-17 19:29:28 -08:00
Henry Cook
08dcf4c6ca
refactor cache params
2014-12-17 14:28:05 -08:00
Henry Cook
d29793d1f7
cleanup CoherenceMetadata and coherence params
2014-12-15 19:23:38 -08:00
Henry Cook
c9320862ae
add l2 dmem signal to rocc
2014-12-12 16:55:08 -08:00
Henry Cook
72ea24283b
multibeat TL; passes all tests
2014-12-12 16:54:33 -08:00
Christopher Celio
f19b3ca43e
Deleted extra spaces at EOL in ctrl.scala
2014-11-16 22:04:33 -08:00
Christopher Celio
6749f67b7f
Fixed BHT update error.
...
- separated out BTB/BHT update
- BHT updates counters on every branch
- BTB update only on mispredicted and taken branches
2014-11-16 22:02:27 -08:00
Henry Cook
b7b2923bff
Cleanup MSHR internal bundles
2014-11-11 18:18:35 -08:00
Henry Cook
c9e7874818
Major tilelink revision for uncached message types
2014-11-11 17:36:48 -08:00
Christopher Celio
fea31d2167
Significant changes and fixes to BTB for superscalar fetch.
...
- BTBUpdate only occurs on mispredicts now.
- RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
Decode).
- Added optional 2nd CAM port to BTB for updates (for when updates to the
BTB may occur out-of-order).
- Fixed resp.mask bit logic.
2014-11-11 03:34:05 -08:00
Henry Cook
bf901e4bca
Remove master_xact_id from Release
2014-11-06 12:09:45 -08:00
Christopher Celio
3be3cd7731
Fixed error with icache/btb resp mask.
2014-11-03 01:13:22 -08:00
Christopher Celio
08d2c13330
Fixed btb/icache bugs regarding resp mask, fw==1
2014-10-20 18:45:23 -07:00
Christopher Celio
91efdc379b
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Also fixed bridx logic and zero-width wire logic.
Conflicts:
src/main/scala/btb.scala
2014-10-14 18:10:29 -07:00
Andrew Waterman
7bb7299018
Don't pollute BTB with PC+4 target predictions
2014-10-14 17:28:37 -07:00
Christopher Celio
59eb7d194d
Finalize superscalar btb.
2014-10-03 16:08:08 -07:00
Andrew Waterman
cde7c9d869
simplify CSR decoding code
2014-10-03 14:31:26 -07:00
Christopher Celio
99614e37aa
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Conflicts:
src/main/scala/btb.scala
src/main/scala/core.scala
2014-10-03 04:22:58 -07:00
Christopher Celio
9cc35dee9a
Returned history update to fetch.
...
- Global history only contains branches.
- Only update BHT and history on BTB hits.
- Gate off speculative update on stall or icmiss.
- Fixed bug where BHT updates were delayed a cycle.
2014-09-29 21:41:07 -07:00
Christopher Celio
8ccd07cfeb
Moved updating global history from fetch to decode.
...
- No longer update global history in fetch stage.
- Only update global history when instruction is a branch.
- Does allow for the possibility of back-to-back branches to see
slightly different histories on subsequent executions.
2014-09-28 05:16:36 -07:00
Christopher Celio
681b43f398
Bug fixes with global history register.
...
- Updated in fetch speculatively.
* Updates gated off by cpu.resp.fire().
* BTB direction factored into history update.
- All branches update the BHT.
- Each instruction carries history; index into BHT is recomputed by
passing in mem_reg_pc.
2014-09-26 10:39:57 -07:00
Christopher Celio
a71bdbbc54
Update history register in fetch speculatively
2014-09-26 05:42:08 -07:00
Christopher Celio
f917810061
Removed RocketCoreParameters from use.
...
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
- This conflicts with other cores which uses nbdcache.
- RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
2014-09-26 05:14:50 -07:00
Christopher Celio
868e747656
Factored out Rocket specifics from CoreParameters
...
- Added new RocketCoreParameters
- Other cores using Rocket as a library will no longer conflict against
Rocket's requires().
2014-09-25 18:52:58 -07:00
Henry Cook
8eb64205f5
bug fix for nbdcache s2_data
2014-09-25 12:00:20 -07:00
Henry Cook
b55c38cdc7
Remove spurious vec consts
2014-09-25 12:00:20 -07:00
Adam Izraelevitz
3e256439c9
Add abstract class Tile
2014-09-24 13:04:20 -07:00
Christopher Celio
180d3d365d
Expanded front-end to support superscalar fetch.
2014-09-17 14:24:03 -07:00
Yunsup Lee
238f7761f6
update README
2014-09-17 11:23:25 -07:00
Yunsup Lee
8abf62fae3
add LICENSE
2014-09-12 18:06:41 -07:00
Yunsup Lee
25180b71f7
add LICENSE
2014-09-12 15:36:42 -07:00
Andrew Waterman
a999c055ed
Don't take an interrupt when EX stage PC is invalid
...
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch. EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.
h/t Yunsup
2014-09-11 01:46:52 -07:00
Henry Cook
5eb5e9eaf5
Standardize ()=>Module(...) top-level Parameters
2014-09-07 17:54:41 -07:00
Henry Cook
5e2f98747f
Merge branch 'dse'
2014-09-06 06:10:15 -07:00
Scott Beamer
600c5d50a9
better fix with explanation of sbt issue
2014-09-02 15:14:56 -07:00
Scott Beamer
f9922a106b
fixes sbt error during first run
2014-09-02 14:34:36 -07:00
Henry Cook
b42a2ab40a
Final parameter refactor
2014-09-01 13:28:58 -07:00
Adam Izraelevitz
2d6aafc32e
Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD
2014-09-01 11:23:50 -07:00
Sagar Karandikar
83c6c2c9e2
rename refs to zynq-fpga to fpga-zynq
2014-08-29 10:26:48 -07:00
Henry Cook
6a4193cf90
minor cache param cleanup
2014-08-19 11:38:46 -07:00
Henry Cook
2de268b3b1
Cache utility traits. Completely compiles, asm tests hang.
2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467
Full conversion to params. Compiles but does not elaborate.
2014-08-19 11:38:02 -07:00
Adam Izraelevitz
4e6d69892d
Added initial brainstorm for parameter hierarchical flattening, does not compile ;)
2014-08-19 11:37:50 -07:00
Adam Izraelevitz
812353bace
Ported FPU parameters to new Chisel Parameters
2014-08-19 11:37:27 -07:00
Yunsup Lee
4ac8e59b1f
add .gitignore
2014-08-18 19:27:50 -07:00
Yunsup Lee
d520846638
add README and sbt files
2014-08-18 19:23:10 -07:00
Andrew Waterman
7bffc6c586
rename Unsigned.size to Unsigned.clog2
2014-06-14 13:58:07 -07:00
Andrew Waterman
3828c628c3
Remove vestigial control signals
2014-06-14 13:58:07 -07:00
Andrew Waterman
04593d433e
clean up Int <-> Boolean conversion stuff
2014-06-14 13:58:07 -07:00
Andrew Waterman
ac88ded35a
Use ROMs to reduce node count and improve QoR a bit
2014-06-14 13:58:07 -07:00
Andrew Waterman
88899eafe0
Reduce node count a bit
2014-06-14 13:58:07 -07:00
Jim Lawson
0c93567dea
Replace needWidth() with getWidth.
2014-06-13 14:58:52 -07:00
Jim Lawson
de32595fba
Quick change to work with new Width class.
2014-06-13 12:00:50 -07:00
Henry Cook
dab675b231
refactor Metadata, clean and expand coherence API
2014-05-28 16:05:48 -07:00
Andrew Waterman
8bc1c33540
Fix BTB error (requires Chisel update)
2014-05-19 18:56:30 -07:00
Andrew Waterman
cbb37ccc3e
Use Mem instead of Vec[Reg]
2014-05-18 19:25:43 -07:00
Andrew Waterman
e91e12ed88
Fix RoCC accumulator example
2014-05-14 16:17:39 -07:00
Andrew Waterman
4ca152b012
Use BundleWithConf to avoid clone method boilerplate
2014-05-09 19:37:16 -07:00
Andrew Waterman
94c1f01ec6
Deanonymize CSRFile's IO bundle
2014-05-09 19:30:57 -07:00
Andrew Waterman
fd5f419eb1
use getWidth instead of width
2014-05-09 19:30:57 -07:00
Andrew Waterman
0c13c00d08
Reduce node count by avoiding elsewhen :-(
2014-05-09 19:30:57 -07:00
Andrew Waterman
8dcc0cbb53
Fix bug with multiple DecodeLogics per module
2014-05-09 19:30:57 -07:00
Henry Cook
5bc6981414
fix metadata default, add bug TODO
2014-05-06 18:36:22 -07:00
Henry Cook
7d6a642c0c
correct use of function value to initialize MetaDataArray
2014-05-06 13:00:00 -07:00
Henry Cook
7f690dd9c8
parameterize metadataarray
2014-05-01 01:45:45 -07:00
Henry Cook
519b2ea2b6
New metadata result trait
2014-04-26 19:08:56 -07:00
Henry Cook
1b156c6db9
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:18:21 -07:00
Henry Cook
fc825c7103
MetaData & friends moved to uncore/
2014-04-23 16:23:51 -07:00
Henry Cook
f4d326b8d7
Prep in HellaCache for extracting MetaData to uncore
2014-04-23 15:43:31 -07:00
Henry Cook
5c62cff2ce
put replacement policy in uncore and minor nbdcache cleanups
2014-04-22 16:53:20 -07:00
Andrew Waterman
09e2ec1f9e
Fix sign of remainder when dividing by zero
...
h/t chris
2014-04-18 16:32:57 -07:00
Henry Cook
1fa505f9ff
remove superfluous AVec object
2014-04-16 17:19:32 -07:00
Andrew Waterman
3520620fbd
Remove D$ -> BTB path
2014-04-15 23:05:02 -07:00
Andrew Waterman
de492b3cf7
Fix critical path through integer scoreboard
2014-04-15 21:28:13 -07:00
Henry Cook
444d0449e3
io.cnt bug in serializer
2014-04-14 17:13:13 -07:00
Henry Cook
1da8ef2ddf
Added serdes to decouple cache row size from tilelink data size
2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
2014-04-10 12:09:52 -07:00
Stephen Twigg
e90f2484aa
Sync with riscv-opcodes (csr register mapping)
2014-04-08 15:48:37 -07:00
Andrew Waterman
3ed8adf032
Add early out for MUL[W] (not MULH[[S]U])
2014-04-07 23:48:02 -07:00
Andrew Waterman
927287da34
Bypass RAS push/pop
2014-04-07 23:47:53 -07:00
Andrew Waterman
f235fa0db6
Move branch resolution to M stage
2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab
Add return address stack
2014-04-01 15:01:27 -07:00
Andrew Waterman
e3b12e0b85
Make BTB more complexity-effective
...
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices. This makes much larger BTBs feasible. It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
2014-03-25 05:22:04 -07:00
Andrew Waterman
804b09c8c5
Frontend QoR tweaks
2014-03-25 05:20:24 -07:00
Andrew Waterman
6465e2df14
Make Int -> Bool conversions explicit
2014-03-24 04:36:53 -07:00
Andrew Waterman
1b030777ce
Remove vestigial control signal
2014-03-24 04:36:12 -07:00
Andrew Waterman
5996418021
Fix exception behavior of fmin/fmax
2014-03-18 18:36:51 -07:00
Andrew Waterman
54cbf0c4f1
Add (unused) RV32 CSRs
2014-03-15 17:33:17 -07:00
Andrew Waterman
943d7ac80a
Use LinkedHashSet/Map for simpler determinism
2014-03-15 17:31:48 -07:00
Donggyu Kim
53d62cb69d
remove nondeterminism
2014-03-15 16:45:58 -07:00
Andrew Waterman
a0389645b7
New FP encoding; improved FP implementation
2014-03-11 18:58:24 -07:00
Andrew Waterman
00bc1a2293
Add fclass.{s|d} instructions
2014-03-10 16:59:24 -07:00
Yunsup Lee
ac4b3f9f22
print out core id
2014-03-04 23:38:49 -08:00
Andrew Waterman
9f2e16c58a
Fix D$ arbiter for >2 inputs
2014-03-04 16:32:17 -08:00
Andrew Waterman
fa75f6e81e
Fix null pointer exception when HAS_FPU=false
2014-03-04 16:32:09 -08:00
Andrew Waterman
c7110c8389
Make FPU pipeline depths configurable
2014-02-28 13:39:59 -08:00
Yunsup Lee
98b830201a
add wen signal to dasm printf
2014-02-25 03:31:06 -08:00
Yunsup Lee
97b1841fcf
change dcache tag bits to 7
2014-02-22 22:53:04 -08:00
Andrew Waterman
8e3ca609f7
Renumber uarch CSRs into custom CSR space
2014-02-14 17:40:00 -08:00
Andrew Waterman
a09ff9fdc7
Revert to old AUIPC definition
2014-02-10 19:04:42 -08:00
Andrew Waterman
1456170c6d
Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence
2014-02-06 12:01:49 -08:00
Andrew Waterman
eca8c99f44
Ignore rocc interrupt line when no rocc is present
2014-02-06 03:06:55 -08:00
Andrew Waterman
e7a726fbac
Make uarch counters read-only
2014-02-06 01:48:56 -08:00
Quan Nguyen
f021213b1d
Merge remote-tracking branch 'origin/master' into hwacha-port
2014-02-06 00:21:28 -08:00
Andrew Waterman
62e9313aef
Add 16 microarchitectural counters
2014-02-06 00:13:02 -08:00
Yunsup Lee
ff7cae29f7
hookup rocc interrupt and s bit
2014-02-06 00:09:42 -08:00
Yunsup Lee
ab4a3e937b
don't share fma pipes
2014-02-05 14:21:43 -08:00
Stephen Twigg
6a02d15c21
Merge branch 'master' into hwacha-port
2014-02-04 17:05:03 -08:00
Henry Cook
2c2b3a7678
cleanups supporting uncore hierarchy
2014-01-31 12:07:26 -08:00
Andrew Waterman
febd26f505
Correct CSR privilege logic
2014-01-31 01:03:17 -08:00
Stephen Twigg
3c3c469725
Add exception signal to rocc interface
2014-01-28 22:13:16 -08:00
Andrew Waterman
0266c1f76a
Support retirement width > 1 in CSR file
2014-01-24 16:37:40 -08:00
Andrew Waterman
267394d3cc
Fix CSR interlocks
2014-01-24 16:37:40 -08:00
Andrew Waterman
1f986d1c96
Branches don't care about the ALU input/function
2014-01-24 16:37:40 -08:00
Andrew Waterman
a1b7774f5d
Simplify handling of CAUSE register
2014-01-24 16:37:39 -08:00
Christopher Celio
a2be21361e
Allow ICacheConfig to toggle fetch-width.
2014-01-22 16:19:57 -08:00
Andrew Waterman
a7489920ce
Support CSR atomics on all CSRs, not just STATUS
2014-01-21 16:17:39 -08:00
Andrew Waterman
6ba2c1abe5
Use auto-generated CAUSE constants
2014-01-21 15:01:54 -08:00
Andrew Waterman
95de358a96
More of the same FPU fix
...
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
2014-01-17 14:09:30 -08:00
Andrew Waterman
cf38001e98
Fix fmv.s.x -> fsd
2014-01-17 03:52:35 -08:00
Yunsup Lee
30b894c2c4
Merge remote-tracking branch 'origin/master' into hwacha-port
2014-01-16 16:04:48 -08:00
Yunsup Lee
6bbbf36979
push accel/rocket dmem port back to rocket
2014-01-16 16:01:41 -08:00
Andrew Waterman
57f4d89c90
Generate D$ replay_next signals correctly
2014-01-16 00:16:09 -08:00
Andrew Waterman
6ebdc4d94e
Simplify store conditional failure code generation
2014-01-16 00:15:48 -08:00
Andrew Waterman
31060ea8ae
Fix fubar long-latency writeback control logic
...
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
2014-01-14 04:02:43 -08:00
Andrew Waterman
e8486817e6
Clean up formatting (i.e. remove tabs, semicolons)
2014-01-13 21:43:56 -08:00
Andrew Waterman
a50a1f7d50
Clean up multiplier/divider stuff
2014-01-13 21:37:16 -08:00
Andrew Waterman
4d236979bd
Fix very far forward JALs
...
We were sign-extending from the wrong bit, causing a backwards jump.
2014-01-13 00:55:48 -08:00
Andrew Waterman
c546f66404
Swap JAL/JALR encodings (again)
2014-01-13 00:54:49 -08:00
Quan Nguyen
ebec444ad2
Increase tag width for configurable precision in Hwacha
2013-12-13 03:33:02 -08:00
Andrew Waterman
07a91bb99a
Miscellaneous cleanup
2013-12-09 19:53:14 -08:00
Andrew Waterman
da3135ac9b
Begin integer unit clean-up
...
...to make it easier to generate the superscalar version of the core.
2013-12-09 15:06:13 -08:00
Andrew Waterman
16d5250924
Correct FP trap behavior on FCSR
2013-12-05 04:18:04 -08:00
Andrew Waterman
5814a90472
Make DecodeLogic interface more flexible
2013-12-05 04:16:48 -08:00
Andrew Waterman
924261e2b2
Update to new privileged ISA... phew
2013-11-25 04:35:15 -08:00
Andrew Waterman
65b8340cea
Mitigate D$ hit -> branch -> NPC critical path
2013-11-24 14:21:03 -08:00
Andrew Waterman
53f726008b
Use Mem instead of Vec[Reg] for TLB
...
QoR-neutral, improves simulation speed
2013-11-24 14:21:02 -08:00
Yunsup Lee
d450b85483
Merge branch 'master', remote-tracking branch 'origin' into hwacha
2013-11-21 14:57:38 -08:00
Yunsup Lee
68e270eeb2
fix slli/slliw encoding bug
2013-11-21 14:44:58 -08:00
Quan Nguyen
3b109763ad
Connect FMA to Hwacha pipes
2013-11-19 20:54:47 -08:00
Stephen Twigg
a662e85f2a
Merge branch 'master' into hwacha
2013-11-14 16:02:44 -08:00
Yunsup Lee
c1966e2b0a
forgot to put htif into uncore package
2013-11-07 15:42:03 -08:00
Yunsup Lee
da033af0b0
move htif to uncore
2013-11-07 13:18:46 -08:00
Yunsup Lee
4c56323f6f
hookup all memory ports
2013-11-05 17:12:09 -08:00
Stephen Twigg
eae571e371
Remove rocc memory simplifye module (Hwacha has its own)
2013-11-05 15:31:03 -08:00
Andrew Waterman
12f0369e6e
Simplify divide early out circuitry
2013-10-29 13:20:40 -07:00
Andrew Waterman
b44dafbdca
Simplify branch offset mux
2013-10-29 13:20:40 -07:00
Andrew Waterman
23f7bab4f3
Reduce FMA pipeline depths
...
FMA QoR has improved enough to allow this change.
2013-10-29 13:20:40 -07:00
Yunsup Lee
1583560757
fix replay bug, don't respond when cmd is a NOP
2013-10-28 22:35:18 -07:00
Stephen Twigg
36b85b8ee2
Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached.
2013-09-25 11:51:10 -07:00
Stephen Twigg
891e459625
Export stats pcr register ( #28 currently) to the top-level
2013-09-25 01:16:32 -07:00
Stephen Twigg
730a6ec76b
AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample
2013-09-24 16:32:49 -07:00
Andrew Waterman
81c752de84
Support disabling virtual memory
2013-09-24 13:58:47 -07:00
Andrew Waterman
adc386f889
Turn off virtual memory inside RoCC base class
2013-09-24 13:58:47 -07:00
Stephen Twigg
3532ae0b79
From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
2013-09-24 10:54:09 -07:00
Stephen Twigg
db1e09f0d0
Fix issues with RoCC AccumulatorExample stalls on memory interface
2013-09-23 00:21:43 -07:00
Stephen Twigg
158cee08af
Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)
2013-09-22 03:18:06 -07:00
Andrew Waterman
1d2f4f8437
New ISA encoding, AUIPC semantics
2013-09-21 06:32:40 -07:00
Andrew Waterman
25ab402932
swap JAL, JALR encodings
2013-09-15 04:29:06 -07:00
Andrew Waterman
110e53cb48
Revert "Add early out to multiplier"
...
This broke recently and I don't have time to figure out why.
2013-09-15 04:15:32 -07:00
Andrew Waterman
88d1c47665
don't disassemble within chisel
2013-09-15 04:14:45 -07:00
Andrew Waterman
f12bbc1e43
working RoCC AccumulatorExample
2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7
Move store data generation into cache
2013-09-14 16:15:07 -07:00
Andrew Waterman
a0cb711451
Start adding RoCC
2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f
Remove Hwacha from Rocket
...
Soon it will use the coprocessor interface.
2013-09-12 22:34:38 -07:00
Andrew Waterman
1edb1e2a0a
Ignore LSB of PC
2013-09-12 17:55:58 -07:00
Andrew Waterman
59f5358435
Implement AQ/RL; move fence logic out of cache
2013-09-12 16:07:30 -07:00
Andrew Waterman
243c4ae342
sync up rocket with new isa
2013-09-12 03:44:38 -07:00
Andrew Waterman
95dd0d8be1
Remove DebugIO/error mode
2013-09-11 20:15:21 -07:00
Henry Cook
f9b85d8158
NetworkIOs no longer use thunks
2013-09-10 16:15:19 -07:00
Henry Cook
d06e24ac24
new enum syntax
2013-09-10 10:51:35 -07:00
Stephen Twigg
cfbfa6b895
Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
2013-09-05 19:22:34 -07:00
Stephen Twigg
d896ccbd43
Merge branch 'master' into chisel-v2
...
Conflicts:
src/main/scala/htif.scala
2013-09-05 16:11:53 -07:00
Andrew Waterman
b9f6e1a7ec
Don't update BTB when garbage was fetched
2013-08-26 14:53:04 -07:00
Yunsup Lee
44e92edf92
fix scr parameterization bug
2013-08-24 22:42:51 -07:00
Andrew Waterman
3895b75a56
Support non-power-of-2 BTBs; prefer invalid entries
2013-08-24 17:33:11 -07:00
Yunsup Lee
2ca5127785
parameterize number of SCRs
2013-08-24 15:47:14 -07:00
Andrew Waterman
daf23b8f79
Add early out to multiplier
2013-08-24 14:44:23 -07:00
Andrew Waterman
67f80ba4b2
Stall div/mul writeback until WB slot is free
2013-08-24 14:44:17 -07:00
Andrew Waterman
d1b5076fee
Don't update BTB when garbage was fetched
2013-08-24 14:44:11 -07:00
Andrew Waterman
52e31f3298
Bypass scoreboard updates
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This reduces div/mul/D$ miss latency by 1 cycle.
2013-08-24 14:44:04 -07:00
Andrew Waterman
d4a0db4575
Reflect ISA changes
2013-08-24 14:43:55 -07:00
Henry Cook
ff7b486006
standardized sbt build
2013-08-15 18:13:19 -07:00
Henry Cook
ae02ebd153
Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
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Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
2013-08-15 16:35:27 -07:00
Henry Cook
3a266cbbfa
final Reg changes
2013-08-15 15:28:15 -07:00
Henry Cook
b570435847
Reg standardization
2013-08-13 17:50:02 -07:00
Henry Cook
858169917e
removed dummy DNCs handled by pruning
2013-08-12 22:34:46 -07:00
Henry Cook
d9b3c7cfc8
Moved RenEn to ChiselUtil
2013-08-12 22:18:25 -07:00
Huy Vo
387cf0ebe0
reset -> resetVal, getReset -> reset
2013-08-12 20:51:54 -07:00
Henry Cook
1a9e43aa11
initial attempt at upgrade
2013-08-12 10:39:11 -07:00
Henry Cook
de313d97de
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2013-08-02 16:30:09 -07:00
Henry Cook
4eaab214d2
Fold uncore constants into TileLinkConfiguration, update coherence API
2013-08-02 16:29:51 -07:00
Henry Cook
bef6c1db35
minor nbdcache cleanup
2013-08-02 16:29:37 -07:00
Stephen Twigg
3132db4f90
Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
2013-07-30 16:36:28 -07:00
Henry Cook
9abdf4e154
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
2013-07-23 20:27:58 -07:00
Henry Cook
5c00d0a030
new tilelink arbiter type
2013-07-09 15:31:46 -07:00
Andrew Waterman
7cc53c7725
clean up Str
2013-06-15 00:45:53 -07:00
Andrew Waterman
95c5147dc5
Add RISC-V instruction disassembler
2013-06-13 10:31:04 -07:00
Henry Cook
569d8fd796
Merge branch 'tilelink-data'
2013-05-23 14:14:40 -07:00
Henry Cook
12205b9684
remove obsolete config file reader prototype
2013-05-23 14:09:03 -07:00
Andrew Waterman
fe9adfe71b
Simplify and correct integer multiplier
2013-05-22 17:27:50 -07:00
Yunsup Lee
11133d6d4c
clock gate s2 registers in the frontend
2013-05-21 18:59:21 -07:00
Yunsup Lee
c837c1d800
fix bug in previous JALR commit
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on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
2013-05-21 18:28:44 -07:00
Henry Cook
69b508ff39
ported caches and htif to use new tilelink
2013-05-21 17:21:04 -07:00
Andrew Waterman
28f914c3f2
don't JALR to speculatively-bypassed addresses
...
Technically not necessary, but probably improves performance.
2013-05-21 16:56:58 -07:00
Yunsup Lee
dcde377303
Fix DM I$ deadlock
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BTB predictions were causing infinite miss loops
2013-05-20 15:22:58 -07:00
Andrew Waterman
3a1b5f01b2
don't take interrupts while they're disabled!
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a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
2013-05-19 23:27:47 -07:00
Andrew Waterman
6eb4c2542a
comment out I$ assert for now
2013-05-18 18:09:23 -07:00
Andrew Waterman
1dab984231
use UFix instead of Bits for arithmetic
2013-05-18 00:45:29 -07:00
Andrew Waterman
dfa7a03f73
use assert, not Assert
2013-05-18 00:45:13 -07:00
Andrew Waterman
d405ffa949
assume all I$ grants bear data
2013-05-01 21:01:20 -07:00
Andrew Waterman
474d321cc7
fix meta hazard counter to reset on new meta writes
2013-05-01 16:35:24 -07:00
Andrew Waterman
a6a88fce19
Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
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This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
2013-05-01 16:34:45 -07:00
Andrew Waterman
63a38e7982
Revert "temp"
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This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
2013-05-01 16:34:33 -07:00
Henry Cook
b6945408cb
temp
2013-05-01 10:24:36 -07:00
Henry Cook
722bc917d3
broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
2013-05-01 10:05:54 -07:00
Andrew Waterman
1501e90c1f
interlock probe unit on tag RAW hazards
2013-04-30 00:38:22 -07:00
Henry Cook
e8b20f3d38
clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
2013-04-25 17:41:04 -07:00
Andrew Waterman
50ccc20bf3
replace RDNPC with AUIPC
2013-04-22 04:20:15 -07:00
Henry Cook
db5a060c7d
fix io dir
2013-04-10 13:47:30 -07:00
Andrew Waterman
ae7720e284
guarantee LR/SC forward progress
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the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
2013-04-07 19:27:21 -07:00
Andrew Waterman
e74e032c87
simplify MSHR memory response logic
2013-04-06 01:03:37 -07:00
Andrew Waterman
1abb9277db
fix LR/SC atomicity violation
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note, it's still not starvation-free.
2013-04-05 19:13:38 -07:00
Andrew Waterman
8cbdeb2abf
add LR/SC support
2013-04-04 17:07:09 -07:00
Andrew Waterman
fc46daecf6
don't flush pipeline on writes to side-effect-free PCRs
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notably, K0, K1, and EPC
2013-04-04 17:07:09 -07:00
Andrew Waterman
8b439ef20d
only support setpcr/clearpcr of SR
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the full PCR RMW support was wasted area/power
2013-04-04 17:07:08 -07:00
Andrew Waterman
d43f484feb
take interrupts on nonzero fromhost values
2013-04-04 17:07:08 -07:00
Andrew Waterman
d4a3351cfc
expose pending interrupts in status register
2013-04-04 17:07:08 -07:00
Henry Cook
f8aebcbf8c
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
2013-04-04 15:50:29 -07:00
Henry Cook
16113a96ba
fixes after merge
2013-03-25 19:09:08 -07:00
Henry Cook
95f0a688e9
Merge branch 'release-xacts'
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Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
2013-03-20 17:37:50 -07:00
Henry Cook
273bd34091
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
2013-03-20 15:53:36 -07:00
Henry Cook
6d2541aced
nTiles -> nClients in LogicalNetworkConfig
2013-03-20 14:12:36 -07:00
Andrew Waterman
ea9d0b771e
remove aborts; simplify probes
2013-03-19 15:29:40 -07:00
Yunsup Lee
0f50970913
move HellaQueue to uncore
2013-03-19 00:43:20 -07:00
Henry Cook
e0361840bd
writebacks on release network pass asm tests and bmarks
2013-02-28 18:11:40 -08:00
Andrew Waterman
35349d227f
update to new Mem style
2013-02-20 16:09:46 -08:00
Andrew Waterman
9f89c812b7
fix HTIF memory size reporting
2013-01-29 23:08:25 -08:00
Yunsup Lee
a0bd0adeb2
change write/read port ordering for vlsi_mem_gen script
2013-01-29 21:32:42 -08:00
Andrew Waterman
66eb3720a4
fix SRAM semantics bug in HellaFlowQueue
2013-01-29 21:16:42 -08:00
Yunsup Lee
60bd3a6413
Revert "shuffled FPU control logic around to make functional unit retiming work better"
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This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
2013-01-29 19:34:55 -08:00
Andrew Waterman
6275e009f8
fix HellaQueue deq.valid signal
2013-01-28 20:57:43 -08:00
Andrew Waterman
45d8066f45
add HellaQueue, an SRAM-based queue
2013-01-28 20:54:25 -08:00
Andrew Waterman
37c67f1d87
pipeline reset to the vector unit
2013-01-28 17:56:32 -08:00
Rimas Avizienis
f2df6147df
shuffled FPU control logic around to make functional unit retiming work better
2013-01-28 17:17:09 -08:00
Henry Cook
f5729c9f25
removed ack_required field from grant messages
2013-01-28 16:44:17 -08:00
Henry Cook
8cbd316b5e
Merge branch 'ready-sig-fix' into pin-cleanup
2013-01-27 23:04:58 -08:00
Henry Cook
931cffa749
ready signal fix
2013-01-27 23:04:35 -08:00
Henry Cook
83c207c852
pin cleanup in htif
2013-01-27 12:00:28 -08:00
Henry Cook
409b549d3c
actually cleared up tile ios
2013-01-27 11:27:09 -08:00
Henry Cook
696dd102eb
cleans up unconnected tile io pins (networking headers overwritten at top level)
2013-01-27 10:59:41 -08:00
Andrew Waterman
c890099e09
add System Control Register space to HTIF
2013-01-24 23:41:24 -08:00
Andrew Waterman
575bd3445a
re-generalize scoreboard
2013-01-24 18:00:39 -08:00
Andrew Waterman
1fbc20450e
don't allow simultaneous reads and writes to the tag ram
2013-01-24 17:55:00 -08:00
Andrew Waterman
37ee843b2c
don't use reset combinationally
2013-01-24 17:55:00 -08:00
Andrew Waterman
bb6fbddf1f
don't probe the mshr file to inquire about refills
2013-01-24 17:54:59 -08:00
Andrew Waterman
5b9f938263
correctly sign-extend badvaddr, epc, and ebase
2013-01-24 17:54:59 -08:00
Rimas Avizienis
63060bc0a8
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
2013-01-23 19:27:53 -08:00
Henry Cook
6b00e7ff74
New TileLink bundle names
2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d
Refactored packet headers/payloads
2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114
standardize IO naming convention
2013-01-07 13:41:36 -08:00
Henry Cook
261e14f831
Refactored uncore conf
2013-01-07 13:41:36 -08:00
Andrew Waterman
78868f6075
add config option to trade mul/div area for speed
2013-01-06 03:47:17 -08:00
Andrew Waterman
ce9f4881d2
remove broken multiplier early out
2013-01-06 03:47:00 -08:00
Andrew Waterman
05f19b21d0
merge multiplier and divider
2012-12-12 02:22:47 -08:00
Andrew Waterman
c921fc34a9
merge ALU left and right shifters
2012-12-12 02:22:34 -08:00
Andrew Waterman
f5c53ce35d
add ecc support to d$ data rams
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i haven't injected errors yet; it may well be incorrect.
2012-12-11 15:58:53 -08:00
Andrew Waterman
3f59e439ef
fix d$ tag raw hazard
2012-12-07 15:14:20 -08:00
Andrew Waterman
e9752f1d72
pipeline host pcr access
2012-12-06 14:22:07 -08:00
Andrew Waterman
4dda38204f
fix d$ reset bug
2012-12-06 03:13:22 -08:00
Andrew Waterman
290d3d226c
fix AMO and store bypass bugs
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thanks, torture tester
2012-12-06 02:07:52 -08:00
Andrew Waterman
4608660f6e
torture revealed a couple bugs
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FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
2012-12-04 05:57:53 -08:00
Andrew Waterman
90cae54ac4
fix D$ read/write concurrency bug
2012-11-27 02:42:27 -08:00
Andrew Waterman
9c857b83f0
refactor PCR file
2012-11-27 01:28:06 -08:00
Andrew Waterman
64674d4d39
clean up PTW and support PADDR_BITS < VADDR_BITS
2012-11-26 20:38:45 -08:00