Don't pollute BTB with PC+4 target predictions
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cde7c9d869
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@ -75,7 +75,7 @@ class BTBUpdate extends Bundle with BTBParameters {
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val isJump = Bool()
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val isCall = Bool()
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val isReturn = Bool()
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val incorrectTarget = Bool()
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val mispredict = Bool()
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}
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class BTBResp extends Bundle with BTBParameters {
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@ -138,8 +138,8 @@ class BTB extends Module with BTBParameters {
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}
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val updateHit = r_update.bits.prediction.valid
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val updateValid = r_update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && r_update.bits.incorrectTarget
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val updateValid = r_update.bits.mispredict || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && r_update.bits.mispredict && r_update.bits.taken
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = updateTarget && !useUpdatePageHit
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@ -208,7 +208,7 @@ class BTB extends Module with BTBParameters {
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val update_btb_hit = io.update.bits.prediction.valid
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when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
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bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht,
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io.update.bits.taken, io.update.bits.incorrectTarget)
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io.update.bits.taken, io.update.bits.mispredict)
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}
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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@ -652,11 +652,11 @@ class Control extends Module
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Mux(replay_wb, PC_WB, // replay
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PC_MEM)))
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io.imem.btb_update.valid := mem_reg_branch || mem_reg_jal || mem_reg_jalr
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io.imem.btb_update.valid := (mem_reg_branch || io.imem.btb_update.bits.isJump) && !take_pc_wb
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io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
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io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
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io.imem.btb_update.bits.taken := mem_reg_jal || mem_reg_branch && io.dpath.mem_br_taken
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io.imem.btb_update.bits.incorrectTarget := take_pc_mem
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io.imem.btb_update.bits.taken := mem_reg_branch && io.dpath.mem_br_taken || io.imem.btb_update.bits.isJump
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io.imem.btb_update.bits.mispredict := take_pc_mem
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io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr
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io.imem.btb_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0)
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io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra
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